An appropriate device figure of merit for bipolar CML

The effects of base resistance, base transit time, and junction capacitances play a key role in the propagation delay of high-speed bipolar logic gates. A simple device figure of merit for transistors used in current mode logic (CML) circuits, based on minimum propagation delay, is developed. This d...

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Bibliographic Details
Published in:IEEE electron device letters 1991-01, Vol.12 (1), p.18-20
Main Author: Greeneich, E.W.
Format: Article
Language:English
Subjects:
Applied sciences
Bipolar transistors
Capacitance
Capacitors
Circuit properties
Cutoff frequency
Delay effects
Electric, optical and optoelectronic circuits
Electronics
Exact sciences and technology
Logic circuits
Logic devices
Logic gates
Magneto electrical resistivity imaging technique
Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits
Propagation delay
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Summary:The effects of base resistance, base transit time, and junction capacitances play a key role in the propagation delay of high-speed bipolar logic gates. A simple device figure of merit for transistors used in current mode logic (CML) circuits, based on minimum propagation delay, is developed. This delay is derived from the large-signal 3-dB cutoff frequency of the CML gate. Results are shown to be applicable for a wide range of device and circuit parameters.< >
ISSN:0741-3106
1558-0563
DOI:10.1109/55.75684