Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/...

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Bibliographic Details
Published in:IEEE electron device letters 2004-05, Vol.25 (5), p.268-270
Main Authors: Shiyang Zhu, Yu, H.Y., Whang, S.J., Chen, J.H., Chen Shen, Chunxiang Zhu, Lee, S.J., Li, M.F., Chan, D.S.H., Yoo, W.J., Du, A., Tung, C.H., Singh, J., Chin, A., Kwong, D.L.
Format: Article
Language:English
Subjects:
Annealing
Budgeting
CMOS
CMOS technology
Dielectrics
Drains
Electrodes
Gates
Hafnium oxide
Laboratories
Microelectronics
MOSFETs
Silicides
Silicon
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Summary:This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2004.826569