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Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode
This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/...
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| Published in: | IEEE electron device letters 2004-05, Vol.25 (5), p.268-270 |
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| Main Authors: | , , , , , , , , , , , , , , |
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| Language: | English |
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| container_end_page | 270 |
| container_issue | 5 |
| container_start_page | 268 |
| container_title | IEEE electron device letters |
| container_volume | 25 |
| creator | Shiyang Zhu Yu, H.Y. Whang, S.J. Chen, J.H. Chen Shen Chunxiang Zhu Lee, S.J. Li, M.F. Chan, D.S.H. Yoo, W.J. Du, A. Tung, C.H. Singh, J. Chin, A. Kwong, D.L. |
| description | This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology. |
| doi_str_mv | 10.1109/LED.2004.826569 |
| format | article |
| fullrecord | <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_proquest_miscellaneous_29025940</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1295103</ieee_id><sourcerecordid>28552667</sourcerecordid><originalsourceid>FETCH-LOGICAL-i294t-7554ba3e94bd4e8e6783a78b353f49f6f3f468adaf5cb3cda65d10b59d602c9a3</originalsourceid><addsrcrecordid>eNqFz71PAjEABfDGaCKis4NL46BTod_XjgbwI8GQiM6X3rXHFQ4O2xLDf-8pTg46veH98pIHwCXBA0KwHk4n4wHFmA8UlULqI9AjQiiEhWTHoIczThAjWJ6CsxiXGBPOM94DL_OyblNa7VFhQvAuwPlwDJ9n8_vJa4QfPtWw9osareDCJAetd40rU_BlhGZj4dol06Dv6lC01p2Dk8o00V38ZB-8dWOjRzSdPTyN7qbIU80TyoTghWFO88Jyp5zMFDOZKphgFdeVrLqQylhTibJgpTVSWIILoa3EtNSG9cHtYXcb2vediylf-1i6pjEb1-5irrSkPMNYdfLmT0k1pkJz_D9UQlApsw5e_4LLdhc23d1cU8K4zOTX2tUBeedcvg1-bcI-J1QLghn7BC35geE</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>921346760</pqid></control><display><type>article</type><title>Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Shiyang Zhu ; Yu, H.Y. ; Whang, S.J. ; Chen, J.H. ; Chen Shen ; Chunxiang Zhu ; Lee, S.J. ; Li, M.F. ; Chan, D.S.H. ; Yoo, W.J. ; Du, A. ; Tung, C.H. ; Singh, J. ; Chin, A. ; Kwong, D.L.</creator><creatorcontrib>Shiyang Zhu ; Yu, H.Y. ; Whang, S.J. ; Chen, J.H. ; Chen Shen ; Chunxiang Zhu ; Lee, S.J. ; Li, M.F. ; Chan, D.S.H. ; Yoo, W.J. ; Du, A. ; Tung, C.H. ; Singh, J. ; Chin, A. ; Kwong, D.L.</creatorcontrib><description>This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2004.826569</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Annealing ; Budgeting ; CMOS ; CMOS technology ; Dielectrics ; Drains ; Electrodes ; Gates ; Hafnium oxide ; Laboratories ; Microelectronics ; MOSFETs ; Silicides ; Silicon</subject><ispartof>IEEE electron device letters, 2004-05, Vol.25 (5), p.268-270</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2004</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1295103$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,54796</link.rule.ids></links><search><creatorcontrib>Shiyang Zhu</creatorcontrib><creatorcontrib>Yu, H.Y.</creatorcontrib><creatorcontrib>Whang, S.J.</creatorcontrib><creatorcontrib>Chen, J.H.</creatorcontrib><creatorcontrib>Chen Shen</creatorcontrib><creatorcontrib>Chunxiang Zhu</creatorcontrib><creatorcontrib>Lee, S.J.</creatorcontrib><creatorcontrib>Li, M.F.</creatorcontrib><creatorcontrib>Chan, D.S.H.</creatorcontrib><creatorcontrib>Yoo, W.J.</creatorcontrib><creatorcontrib>Du, A.</creatorcontrib><creatorcontrib>Tung, C.H.</creatorcontrib><creatorcontrib>Singh, J.</creatorcontrib><creatorcontrib>Chin, A.</creatorcontrib><creatorcontrib>Kwong, D.L.</creatorcontrib><title>Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.</description><subject>Annealing</subject><subject>Budgeting</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>Dielectrics</subject><subject>Drains</subject><subject>Electrodes</subject><subject>Gates</subject><subject>Hafnium oxide</subject><subject>Laboratories</subject><subject>Microelectronics</subject><subject>MOSFETs</subject><subject>Silicides</subject><subject>Silicon</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><recordid>eNqFz71PAjEABfDGaCKis4NL46BTod_XjgbwI8GQiM6X3rXHFQ4O2xLDf-8pTg46veH98pIHwCXBA0KwHk4n4wHFmA8UlULqI9AjQiiEhWTHoIczThAjWJ6CsxiXGBPOM94DL_OyblNa7VFhQvAuwPlwDJ9n8_vJa4QfPtWw9osareDCJAetd40rU_BlhGZj4dol06Dv6lC01p2Dk8o00V38ZB-8dWOjRzSdPTyN7qbIU80TyoTghWFO88Jyp5zMFDOZKphgFdeVrLqQylhTibJgpTVSWIILoa3EtNSG9cHtYXcb2vediylf-1i6pjEb1-5irrSkPMNYdfLmT0k1pkJz_D9UQlApsw5e_4LLdhc23d1cU8K4zOTX2tUBeedcvg1-bcI-J1QLghn7BC35geE</recordid><startdate>20040501</startdate><enddate>20040501</enddate><creator>Shiyang Zhu</creator><creator>Yu, H.Y.</creator><creator>Whang, S.J.</creator><creator>Chen, J.H.</creator><creator>Chen Shen</creator><creator>Chunxiang Zhu</creator><creator>Lee, S.J.</creator><creator>Li, M.F.</creator><creator>Chan, D.S.H.</creator><creator>Yoo, W.J.</creator><creator>Du, A.</creator><creator>Tung, C.H.</creator><creator>Singh, J.</creator><creator>Chin, A.</creator><creator>Kwong, D.L.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope><scope>F28</scope><scope>FR3</scope><scope>KR7</scope></search><sort><creationdate>20040501</creationdate><title>Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode</title><author>Shiyang Zhu ; Yu, H.Y. ; Whang, S.J. ; Chen, J.H. ; Chen Shen ; Chunxiang Zhu ; Lee, S.J. ; Li, M.F. ; Chan, D.S.H. ; Yoo, W.J. ; Du, A. ; Tung, C.H. ; Singh, J. ; Chin, A. ; Kwong, D.L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i294t-7554ba3e94bd4e8e6783a78b353f49f6f3f468adaf5cb3cda65d10b59d602c9a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Annealing</topic><topic>Budgeting</topic><topic>CMOS</topic><topic>CMOS technology</topic><topic>Dielectrics</topic><topic>Drains</topic><topic>Electrodes</topic><topic>Gates</topic><topic>Hafnium oxide</topic><topic>Laboratories</topic><topic>Microelectronics</topic><topic>MOSFETs</topic><topic>Silicides</topic><topic>Silicon</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Shiyang Zhu</creatorcontrib><creatorcontrib>Yu, H.Y.</creatorcontrib><creatorcontrib>Whang, S.J.</creatorcontrib><creatorcontrib>Chen, J.H.</creatorcontrib><creatorcontrib>Chen Shen</creatorcontrib><creatorcontrib>Chunxiang Zhu</creatorcontrib><creatorcontrib>Lee, S.J.</creatorcontrib><creatorcontrib>Li, M.F.</creatorcontrib><creatorcontrib>Chan, D.S.H.</creatorcontrib><creatorcontrib>Yoo, W.J.</creatorcontrib><creatorcontrib>Du, A.</creatorcontrib><creatorcontrib>Tung, C.H.</creatorcontrib><creatorcontrib>Singh, J.</creatorcontrib><creatorcontrib>Chin, A.</creatorcontrib><creatorcontrib>Kwong, D.L.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Civil Engineering Abstracts</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Shiyang Zhu</au><au>Yu, H.Y.</au><au>Whang, S.J.</au><au>Chen, J.H.</au><au>Chen Shen</au><au>Chunxiang Zhu</au><au>Lee, S.J.</au><au>Li, M.F.</au><au>Chan, D.S.H.</au><au>Yoo, W.J.</au><au>Du, A.</au><au>Tung, C.H.</au><au>Singh, J.</au><au>Chin, A.</au><au>Kwong, D.L.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2004-05-01</date><risdate>2004</risdate><volume>25</volume><issue>5</issue><spage>268</spage><epage>270</epage><pages>268-270</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LED.2004.826569</doi><tpages>3</tpages></addata></record> |
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| ispartof | IEEE electron device letters, 2004-05, Vol.25 (5), p.268-270 |
| issn | 0741-3106 1558-0563 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Journals |
| subjects | Annealing Budgeting CMOS CMOS technology Dielectrics Drains Electrodes Gates Hafnium oxide Laboratories Microelectronics MOSFETs Silicides Silicon |
| title | Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T23%3A30%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Schottky-barrier%20S/D%20MOSFETs%20with%20high-k%20gate%20dielectrics%20and%20metal-gate%20electrode&rft.jtitle=IEEE%20electron%20device%20letters&rft.au=Shiyang%20Zhu&rft.date=2004-05-01&rft.volume=25&rft.issue=5&rft.spage=268&rft.epage=270&rft.pages=268-270&rft.issn=0741-3106&rft.eissn=1558-0563&rft.coden=EDLEDZ&rft_id=info:doi/10.1109/LED.2004.826569&rft_dat=%3Cproquest_ieee_%3E28552667%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i294t-7554ba3e94bd4e8e6783a78b353f49f6f3f468adaf5cb3cda65d10b59d602c9a3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=921346760&rft_id=info:pmid/&rft_ieee_id=1295103&rfr_iscdi=true |