Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture

Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f/sub T/ values. In this paper, we demonstrate a device with sub-20 ps t/sub pd/ values even at f/sub T/=23 GHz, a performance which has been achieved by implementing a number of techn...

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Bibliographic Details
Published in:IEEE transactions on electron devices 1995-03, Vol.42 (3), p.399-405
Main Authors: Iinuma, T., Itoh, N., Nakajima, H., Inou, K., Matsuda, S., Yoshino, C., Tsuboi, Y., Katsumata, Y., Iwai, H.
Format: Article
Language:English
Subjects:
Bipolar transistors
Cutoff frequency
Delay effects
Electrodes
Epitaxial growth
Germanium silicon alloys
Parasitic capacitance
Roentgenium
Senior members
Silicon germanium
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Summary:Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f/sub T/ values. In this paper, we demonstrate a device with sub-20 ps t/sub pd/ values even at f/sub T/=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce C/sub CB/, 2) a low-concentration collector design to reduce C/sub CB/, 3) NiSi-salicided base and emitter electrodes to reduce R/sub B/, and 4) a shallow base formed by double diffusion technology for relatively high f/sub T/ with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V.< >
ISSN:0018-9383
1557-9646
DOI:10.1109/16.368035