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Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture
Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f/sub T/ values. In this paper, we demonstrate a device with sub-20 ps t/sub pd/ values even at f/sub T/=23 GHz, a performance which has been achieved by implementing a number of techn...
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| Published in: | IEEE transactions on electron devices 1995-03, Vol.42 (3), p.399-405 |
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| Main Authors: | , , , , , , , , |
| Format: | Article |
| Language: | English |
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| cited_by | cdi_FETCH-LOGICAL-c308t-59ac8c9a90c32178f704b383b5f3ca29cb55622c311c8191928a2b8bbcf63d773 |
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| cites | cdi_FETCH-LOGICAL-c308t-59ac8c9a90c32178f704b383b5f3ca29cb55622c311c8191928a2b8bbcf63d773 |
| container_end_page | 405 |
| container_issue | 3 |
| container_start_page | 399 |
| container_title | IEEE transactions on electron devices |
| container_volume | 42 |
| creator | Iinuma, T. Itoh, N. Nakajima, H. Inou, K. Matsuda, S. Yoshino, C. Tsuboi, Y. Katsumata, Y. Iwai, H. |
| description | Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f/sub T/ values. In this paper, we demonstrate a device with sub-20 ps t/sub pd/ values even at f/sub T/=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce C/sub CB/, 2) a low-concentration collector design to reduce C/sub CB/, 3) NiSi-salicided base and emitter electrodes to reduce R/sub B/, and 4) a shallow base formed by double diffusion technology for relatively high f/sub T/ with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V.< > |
| doi_str_mv | 10.1109/16.368035 |
| format | article |
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In this paper, we demonstrate a device with sub-20 ps t/sub pd/ values even at f/sub T/=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce C/sub CB/, 2) a low-concentration collector design to reduce C/sub CB/, 3) NiSi-salicided base and emitter electrodes to reduce R/sub B/, and 4) a shallow base formed by double diffusion technology for relatively high f/sub T/ with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V.< ></description><subject>Bipolar transistors</subject><subject>Cutoff frequency</subject><subject>Delay effects</subject><subject>Electrodes</subject><subject>Epitaxial growth</subject><subject>Germanium silicon alloys</subject><subject>Parasitic capacitance</subject><subject>Roentgenium</subject><subject>Senior members</subject><subject>Silicon germanium</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1995</creationdate><recordtype>article</recordtype><recordid>eNqF0E1LAzEQBuAgCtbqwaunnAQPqfne5CilfmDBg3oOSZp1I9vummQp_ntXtnj1NAzzMMy8AFwSvCAE61siF0wqzMQRmBEhKqQll8dghjFRSDPFTsFZzp9jKzmnM_D8OjhEMewzbOJHg3IfwgaulmvoYt-1NsGS7C7HXLoE97E0sO32sLfJ5liihzb5Jpbgy5DCOTipbZvDxaHOwfv96m35iNYvD0_LuzXyDKuChLZeeW019oySStUV5m68zImaeUu1d0JISj0jxCuiiabKUqec87Vkm6pic3A97e1T9zWEXMw2Zh_a1u5CN2RDNeZ8fP5_qASveKVHeDNBn7qcU6hNn-LWpm9DsPnN1RBpplxHezXZGEL4c4fhD1macU0</recordid><startdate>19950301</startdate><enddate>19950301</enddate><creator>Iinuma, T.</creator><creator>Itoh, N.</creator><creator>Nakajima, H.</creator><creator>Inou, K.</creator><creator>Matsuda, S.</creator><creator>Yoshino, C.</creator><creator>Tsuboi, Y.</creator><creator>Katsumata, Y.</creator><creator>Iwai, H.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope></search><sort><creationdate>19950301</creationdate><title>Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture</title><author>Iinuma, T. ; Itoh, N. ; Nakajima, H. ; Inou, K. ; Matsuda, S. ; Yoshino, C. ; Tsuboi, Y. ; Katsumata, Y. ; Iwai, H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c308t-59ac8c9a90c32178f704b383b5f3ca29cb55622c311c8191928a2b8bbcf63d773</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Bipolar transistors</topic><topic>Cutoff frequency</topic><topic>Delay effects</topic><topic>Electrodes</topic><topic>Epitaxial growth</topic><topic>Germanium silicon alloys</topic><topic>Parasitic capacitance</topic><topic>Roentgenium</topic><topic>Senior members</topic><topic>Silicon germanium</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Iinuma, T.</creatorcontrib><creatorcontrib>Itoh, N.</creatorcontrib><creatorcontrib>Nakajima, H.</creatorcontrib><creatorcontrib>Inou, K.</creatorcontrib><creatorcontrib>Matsuda, S.</creatorcontrib><creatorcontrib>Yoshino, C.</creatorcontrib><creatorcontrib>Tsuboi, Y.</creatorcontrib><creatorcontrib>Katsumata, Y.</creatorcontrib><creatorcontrib>Iwai, H.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Iinuma, T.</au><au>Itoh, N.</au><au>Nakajima, H.</au><au>Inou, K.</au><au>Matsuda, S.</au><au>Yoshino, C.</au><au>Tsuboi, Y.</au><au>Katsumata, Y.</au><au>Iwai, H.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>1995-03-01</date><risdate>1995</risdate><volume>42</volume><issue>3</issue><spage>399</spage><epage>405</epage><pages>399-405</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f/sub T/ values. In this paper, we demonstrate a device with sub-20 ps t/sub pd/ values even at f/sub T/=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce C/sub CB/, 2) a low-concentration collector design to reduce C/sub CB/, 3) NiSi-salicided base and emitter electrodes to reduce R/sub B/, and 4) a shallow base formed by double diffusion technology for relatively high f/sub T/ with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V.< ></abstract><pub>IEEE</pub><doi>10.1109/16.368035</doi><tpages>7</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 1995-03, Vol.42 (3), p.399-405 |
| issn | 0018-9383 1557-9646 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_29044155 |
| source | IEEE Electronic Library (IEL) Journals |
| subjects | Bipolar transistors Cutoff frequency Delay effects Electrodes Epitaxial growth Germanium silicon alloys Parasitic capacitance Roentgenium Senior members Silicon germanium |
| title | Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture |
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