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Spin coating over topography
A model for predicting film thickness profiles around topographical features during spin coating is presented. This model is applicable to features of arbitrary geometry in the two lateral dimensions. This generally permits study of the planarization of real device structures, including both isolate...
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Published in: | IEEE transactions on semiconductor manufacturing 1993-02, Vol.6 (1), p.72-76 |
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container_title | IEEE transactions on semiconductor manufacturing |
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creator | Peurrung, L.M. Graves, D.B. |
description | A model for predicting film thickness profiles around topographical features during spin coating is presented. This model is applicable to features of arbitrary geometry in the two lateral dimensions. This generally permits study of the planarization of real device structures, including both isolated and neighboring features, with any orientation with respect to the wafer center. Predictions from this model agree qualitatively with measured thin-film profiles from interferograms taken during spinning. Phenomena such as pile-up and wakes result from interactions between surface tension and other driving forces in the flow.< > |
doi_str_mv | 10.1109/66.210660 |
format | article |
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This model is applicable to features of arbitrary geometry in the two lateral dimensions. This generally permits study of the planarization of real device structures, including both isolated and neighboring features, with any orientation with respect to the wafer center. Predictions from this model agree qualitatively with measured thin-film profiles from interferograms taken during spinning. Phenomena such as pile-up and wakes result from interactions between surface tension and other driving forces in the flow.< ></description><identifier>ISSN: 0894-6507</identifier><identifier>EISSN: 1558-2345</identifier><identifier>DOI: 10.1109/66.210660</identifier><identifier>CODEN: ITSMED</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Coatings ; Electric network topology ; Electronics ; Equations ; Exact sciences and technology ; Fluid dynamics ; Geometry ; Lithography ; Mathematical models ; Microelectronic fabrication (materials and surfaces technology) ; Planarization ; Predictive models ; Resists ; Semiconductor device modeling ; Semiconductor device models ; Semiconductor device structures ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Spinning ; Surface tension ; Surface topography ; Thickness control ; WSI circuits</subject><ispartof>IEEE transactions on semiconductor manufacturing, 1993-02, Vol.6 (1), p.72-76</ispartof><rights>1993 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c400t-2b2280134dd03ec04ecc26320f28cf1b3989ddc930517bb59126956b71e57f7a3</citedby><cites>FETCH-LOGICAL-c400t-2b2280134dd03ec04ecc26320f28cf1b3989ddc930517bb59126956b71e57f7a3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/210660$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,27923,27924,54795</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=4585161$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Peurrung, L.M.</creatorcontrib><creatorcontrib>Graves, D.B.</creatorcontrib><title>Spin coating over topography</title><title>IEEE transactions on semiconductor manufacturing</title><addtitle>TSM</addtitle><description>A model for predicting film thickness profiles around topographical features during spin coating is presented. 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Phenomena such as pile-up and wakes result from interactions between surface tension and other driving forces in the flow.< ></description><subject>Applied sciences</subject><subject>Coatings</subject><subject>Electric network topology</subject><subject>Electronics</subject><subject>Equations</subject><subject>Exact sciences and technology</subject><subject>Fluid dynamics</subject><subject>Geometry</subject><subject>Lithography</subject><subject>Mathematical models</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>Planarization</subject><subject>Predictive models</subject><subject>Resists</subject><subject>Semiconductor device modeling</subject><subject>Semiconductor device models</subject><subject>Semiconductor device structures</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Spinning</subject><subject>Surface tension</subject><subject>Surface topography</subject><subject>Thickness control</subject><subject>WSI circuits</subject><issn>0894-6507</issn><issn>1558-2345</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1993</creationdate><recordtype>article</recordtype><recordid>eNqF0D1PwzAQBmALgUQpDKyIoQMCMaScv872iCq-pEoMwBw5jlOC0jjYKVL_Pa1SdYTphnvu1ekl5JzClFIwd4hTRgERDsiISqkzxoU8JCPQRmQoQR2Tk5S-AKgQRo3I5VtXtxMXbF-3i0n48XHShy4sou0-16fkqLJN8me7OSYfjw_vs-ds_vr0MrufZ04A9BkrGNNAuShL4N6B8M4x5Awqpl1FC260KUtnOEiqikIaytBILBT1UlXK8jG5GXK7GL5XPvX5sk7ON41tfVilXAmJSnKlN_L6T8kMCIWC_g81AhcC_ofIBBMaN_B2gC6GlKKv8i7WSxvXOYV8232OmA_db-zVLtQmZ5sq2tbVaX8gpJYUt09eDKz23u-3u4xfEQiHjg</recordid><startdate>19930201</startdate><enddate>19930201</enddate><creator>Peurrung, L.M.</creator><creator>Graves, D.B.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope><scope>7TB</scope><scope>FR3</scope><scope>H8D</scope><scope>KR7</scope><scope>7TC</scope></search><sort><creationdate>19930201</creationdate><title>Spin coating over topography</title><author>Peurrung, L.M. ; Graves, D.B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c400t-2b2280134dd03ec04ecc26320f28cf1b3989ddc930517bb59126956b71e57f7a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Applied sciences</topic><topic>Coatings</topic><topic>Electric network topology</topic><topic>Electronics</topic><topic>Equations</topic><topic>Exact sciences and technology</topic><topic>Fluid dynamics</topic><topic>Geometry</topic><topic>Lithography</topic><topic>Mathematical models</topic><topic>Microelectronic fabrication (materials and surfaces technology)</topic><topic>Planarization</topic><topic>Predictive models</topic><topic>Resists</topic><topic>Semiconductor device modeling</topic><topic>Semiconductor device models</topic><topic>Semiconductor device structures</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Spinning</topic><topic>Surface tension</topic><topic>Surface topography</topic><topic>Thickness control</topic><topic>WSI circuits</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Peurrung, L.M.</creatorcontrib><creatorcontrib>Graves, D.B.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Engineering Research Database</collection><collection>Aerospace Database</collection><collection>Civil Engineering Abstracts</collection><collection>Mechanical Engineering Abstracts</collection><jtitle>IEEE transactions on semiconductor manufacturing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Peurrung, L.M.</au><au>Graves, D.B.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Spin coating over topography</atitle><jtitle>IEEE transactions on semiconductor manufacturing</jtitle><stitle>TSM</stitle><date>1993-02-01</date><risdate>1993</risdate><volume>6</volume><issue>1</issue><spage>72</spage><epage>76</epage><pages>72-76</pages><issn>0894-6507</issn><eissn>1558-2345</eissn><coden>ITSMED</coden><abstract>A model for predicting film thickness profiles around topographical features during spin coating is presented. This model is applicable to features of arbitrary geometry in the two lateral dimensions. This generally permits study of the planarization of real device structures, including both isolated and neighboring features, with any orientation with respect to the wafer center. Predictions from this model agree qualitatively with measured thin-film profiles from interferograms taken during spinning. Phenomena such as pile-up and wakes result from interactions between surface tension and other driving forces in the flow.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/66.210660</doi><tpages>5</tpages></addata></record> |
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ispartof | IEEE transactions on semiconductor manufacturing, 1993-02, Vol.6 (1), p.72-76 |
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source | IEEE Electronic Library (IEL) Journals |
subjects | Applied sciences Coatings Electric network topology Electronics Equations Exact sciences and technology Fluid dynamics Geometry Lithography Mathematical models Microelectronic fabrication (materials and surfaces technology) Planarization Predictive models Resists Semiconductor device modeling Semiconductor device models Semiconductor device structures Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Spinning Surface tension Surface topography Thickness control WSI circuits |
title | Spin coating over topography |
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