Technology scaling effects on multipliers

• Published in: IEEE transactions on computers 1998-11, Vol.47 (11), p.1201-1215
• Main Authors: Al-Twaijry, H.A., Flynn, M.J.
• Format: Article
• Language: English
• Subjects: Adders; Algorithmics. Computability. Computer arithmetics; Applied sciences; Computer aided design; Computer science; control theory; systems; Counting circuits; Delay; Design. Technologies. Operation analysis. Testing; Electronics; Encoding; Exact sciences and technology; Integrated circuit interconnections; Integrated circuit technology; Integrated circuits; Iterative algorithms; Microprocessors; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Software; Theoretical computing; Topology; Tree data structures
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/12.736430

Since integrated circuits were invented, fabrication engineers have been able to steadily decrease the dimensions of the devices (transistors). These reductions in the minimum feature sizes have resulted in improved performance. In addition, the dimensions of the interconnect used to connect the active transistors have also scaled. The decreasing dimensions of the physical devices causes the capacitance and resistances of the different parts of the multiplier to change. Therefore, the relative delay due to each part of the multiplier changes. In addition, the different encoding schemes used to generate the partial products and the different topologies used in the reduction of the partial products effect the total latency of the multiplier. This paper examines the effects of the smaller device dimensions on multipliers. It shows that the interconnect is becoming more important and that automatic generation of partial products provides the minimum latency for small feature sizes.