The first MAJC microprocessor: a dual CPU system-on-a-chip

The first implementation of MAJC architecture achieves high performance by using very long instruction word (VLIW), single instruction multiple data (SIMD), and chip multiprocessing. The chip integrates two processors, a memory controller, two high-speed parallel I/O interfaces, and a PCI controller...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 2001-11, Vol.36 (11), p.1609-1616
Main Authors: Kowalczyk, A., Adler, V., Amir, C., Chiu, F., Choon Ping Chng, De Lange, W.J., Yuefei Ge, Ghosh, S., Tan Canh Hoang, Baoqing Huang, Kant, S., Kao, Y.S., Cong Khieu, Kumar, S., Lan Lee, Liebermensch, A., Xin Liu, Malur, N.G., Martin, A.A., Ngo, H., Sung-Hun Oh, Orginos, I., Shih, L., Sur, B., Tremblay, M., Tzeng, A., Vo, D., Zambere, S., Jin Zong
Format: Article
Language:English
Subjects:
Architecture
Arrays
Assembly
Ceramics
Chip formation
Chips
CMOS process
CMOS technology
Copper
High speed
Microprocessors
Multiprocessing (computers)
Packaging
Process control
Processors
System-on-a-chip
VLIW
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The first implementation of MAJC architecture achieves high performance by using very long instruction word (VLIW), single instruction multiple data (SIMD), and chip multiprocessing. The chip integrates two processors, a memory controller, two high-speed parallel I/O interfaces, and a PCI controller. The chip, fabricated in a 0.22-/spl mu/m CMOS process with six layers of copper interconnect, contains 13 million transistors and operates at 500 MHz. It is packaged in a 624-pin ceramic column grid array using flip-chip assembly technology.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.962280