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64-bit Block ciphers: hardware implementations and comparison analysis
A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide an international encryption standard for the 64-...
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| Published in: | Computers & electrical engineering 2004-11, Vol.30 (8), p.593-604 |
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| Main Authors: | , , , |
| Format: | Article |
| Language: | English |
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| cited_by | cdi_FETCH-LOGICAL-c352t-61a0559e3b5053265deb9a5f918c05aac02846e17a698bf60644a5622d9820b93 |
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| cites | cdi_FETCH-LOGICAL-c352t-61a0559e3b5053265deb9a5f918c05aac02846e17a698bf60644a5622d9820b93 |
| container_end_page | 604 |
| container_issue | 8 |
| container_start_page | 593 |
| container_title | Computers & electrical engineering |
| container_volume | 30 |
| creator | Kitsos, P. Sklavos, N. Galanis, M.D. Koufopavlou, O. |
| description | A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide an international encryption standard for the 64-bit block ciphers. Two basic architectures are implemented for each cipher. For the non-feedback cipher modes, the pipelined technique between the rounds is used, and the achieved throughput ranges from 3.0
Gbps for IDEA to 6.9
Gbps for Triple-DES. For feedback ciphers modes, the basic iterative architecture is considered and the achieved throughput ranges from 115
Mbps for Triple-DES to 462
Mbps for KHAZAD. The throughput, throughput per slice, latency, and area requirement results are provided for all the ciphers implementations. Our study is an effort to determine the most suitable algorithm for hardware implementation with FPGA devices. |
| doi_str_mv | 10.1016/j.compeleceng.2004.11.001 |
| format | article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_29114009</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S0045790605000108</els_id><sourcerecordid>29114009</sourcerecordid><originalsourceid>FETCH-LOGICAL-c352t-61a0559e3b5053265deb9a5f918c05aac02846e17a698bf60644a5622d9820b93</originalsourceid><addsrcrecordid>eNqNkEFPhDAQhRujievqf8CLN3AGaKHedOOqySZe9NyUMrhdgWKLmv33QtaDR0-Tl3nvTeZj7BIhQUBxvUuM6wZqyVD_lqQAeYKYAOARW2BZyBgKzo_ZYlrwuJAgTtlZCDuYtMBywdYijys7RnetM--RscOWfLiJttrX39pTZLuhpY76UY_W9SHSfR3NF7W3wfWT1O0-2HDOThrdBrr4nUv2ur5_WT3Gm-eHp9XtJjYZT8dYoAbOJWUVB56lgtdUSc0biaUBrrWBtMwFYaGFLKtGgMhzzUWa1rJMoZLZkl0degfvPj4pjKqzwVDb6p7cZ1CpRMwBZqM8GI13IXhq1OBtp_1eIaiZnNqpP-TUTE4hqonclF0dsjR98mXJq2As9YZq68mMqnb2Hy0_n5h8ig</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>29114009</pqid></control><display><type>article</type><title>64-bit Block ciphers: hardware implementations and comparison analysis</title><source>Elsevier</source><creator>Kitsos, P. ; Sklavos, N. ; Galanis, M.D. ; Koufopavlou, O.</creator><creatorcontrib>Kitsos, P. ; Sklavos, N. ; Galanis, M.D. ; Koufopavlou, O.</creatorcontrib><description>A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide an international encryption standard for the 64-bit block ciphers. Two basic architectures are implemented for each cipher. For the non-feedback cipher modes, the pipelined technique between the rounds is used, and the achieved throughput ranges from 3.0
Gbps for IDEA to 6.9
Gbps for Triple-DES. For feedback ciphers modes, the basic iterative architecture is considered and the achieved throughput ranges from 115
Mbps for Triple-DES to 462
Mbps for KHAZAD. The throughput, throughput per slice, latency, and area requirement results are provided for all the ciphers implementations. Our study is an effort to determine the most suitable algorithm for hardware implementation with FPGA devices.</description><identifier>ISSN: 0045-7906</identifier><identifier>EISSN: 1879-0755</identifier><identifier>DOI: 10.1016/j.compeleceng.2004.11.001</identifier><language>eng</language><publisher>Elsevier Ltd</publisher><subject>64-bit Block cipher ; Cryptography ; FPGA ; Hardware implementation ; ISO/IEC 18033-3</subject><ispartof>Computers & electrical engineering, 2004-11, Vol.30 (8), p.593-604</ispartof><rights>2005 Elsevier Ltd</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c352t-61a0559e3b5053265deb9a5f918c05aac02846e17a698bf60644a5622d9820b93</citedby><cites>FETCH-LOGICAL-c352t-61a0559e3b5053265deb9a5f918c05aac02846e17a698bf60644a5622d9820b93</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids></links><search><creatorcontrib>Kitsos, P.</creatorcontrib><creatorcontrib>Sklavos, N.</creatorcontrib><creatorcontrib>Galanis, M.D.</creatorcontrib><creatorcontrib>Koufopavlou, O.</creatorcontrib><title>64-bit Block ciphers: hardware implementations and comparison analysis</title><title>Computers & electrical engineering</title><description>A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide an international encryption standard for the 64-bit block ciphers. Two basic architectures are implemented for each cipher. For the non-feedback cipher modes, the pipelined technique between the rounds is used, and the achieved throughput ranges from 3.0
Gbps for IDEA to 6.9
Gbps for Triple-DES. For feedback ciphers modes, the basic iterative architecture is considered and the achieved throughput ranges from 115
Mbps for Triple-DES to 462
Mbps for KHAZAD. The throughput, throughput per slice, latency, and area requirement results are provided for all the ciphers implementations. Our study is an effort to determine the most suitable algorithm for hardware implementation with FPGA devices.</description><subject>64-bit Block cipher</subject><subject>Cryptography</subject><subject>FPGA</subject><subject>Hardware implementation</subject><subject>ISO/IEC 18033-3</subject><issn>0045-7906</issn><issn>1879-0755</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><recordid>eNqNkEFPhDAQhRujievqf8CLN3AGaKHedOOqySZe9NyUMrhdgWKLmv33QtaDR0-Tl3nvTeZj7BIhQUBxvUuM6wZqyVD_lqQAeYKYAOARW2BZyBgKzo_ZYlrwuJAgTtlZCDuYtMBywdYijys7RnetM--RscOWfLiJttrX39pTZLuhpY76UY_W9SHSfR3NF7W3wfWT1O0-2HDOThrdBrr4nUv2ur5_WT3Gm-eHp9XtJjYZT8dYoAbOJWUVB56lgtdUSc0biaUBrrWBtMwFYaGFLKtGgMhzzUWa1rJMoZLZkl0degfvPj4pjKqzwVDb6p7cZ1CpRMwBZqM8GI13IXhq1OBtp_1eIaiZnNqpP-TUTE4hqonclF0dsjR98mXJq2As9YZq68mMqnb2Hy0_n5h8ig</recordid><startdate>20041101</startdate><enddate>20041101</enddate><creator>Kitsos, P.</creator><creator>Sklavos, N.</creator><creator>Galanis, M.D.</creator><creator>Koufopavlou, O.</creator><general>Elsevier Ltd</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20041101</creationdate><title>64-bit Block ciphers: hardware implementations and comparison analysis</title><author>Kitsos, P. ; Sklavos, N. ; Galanis, M.D. ; Koufopavlou, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c352t-61a0559e3b5053265deb9a5f918c05aac02846e17a698bf60644a5622d9820b93</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>64-bit Block cipher</topic><topic>Cryptography</topic><topic>FPGA</topic><topic>Hardware implementation</topic><topic>ISO/IEC 18033-3</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kitsos, P.</creatorcontrib><creatorcontrib>Sklavos, N.</creatorcontrib><creatorcontrib>Galanis, M.D.</creatorcontrib><creatorcontrib>Koufopavlou, O.</creatorcontrib><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>Computers & electrical engineering</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Kitsos, P.</au><au>Sklavos, N.</au><au>Galanis, M.D.</au><au>Koufopavlou, O.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>64-bit Block ciphers: hardware implementations and comparison analysis</atitle><jtitle>Computers & electrical engineering</jtitle><date>2004-11-01</date><risdate>2004</risdate><volume>30</volume><issue>8</issue><spage>593</spage><epage>604</epage><pages>593-604</pages><issn>0045-7906</issn><eissn>1879-0755</eissn><abstract>A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are under consideration from the ISO/IEC 18033-3 standard in order to provide an international encryption standard for the 64-bit block ciphers. Two basic architectures are implemented for each cipher. For the non-feedback cipher modes, the pipelined technique between the rounds is used, and the achieved throughput ranges from 3.0
Gbps for IDEA to 6.9
Gbps for Triple-DES. For feedback ciphers modes, the basic iterative architecture is considered and the achieved throughput ranges from 115
Mbps for Triple-DES to 462
Mbps for KHAZAD. The throughput, throughput per slice, latency, and area requirement results are provided for all the ciphers implementations. Our study is an effort to determine the most suitable algorithm for hardware implementation with FPGA devices.</abstract><pub>Elsevier Ltd</pub><doi>10.1016/j.compeleceng.2004.11.001</doi><tpages>12</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0045-7906 |
| ispartof | Computers & electrical engineering, 2004-11, Vol.30 (8), p.593-604 |
| issn | 0045-7906 1879-0755 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_29114009 |
| source | Elsevier |
| subjects | 64-bit Block cipher Cryptography FPGA Hardware implementation ISO/IEC 18033-3 |
| title | 64-bit Block ciphers: hardware implementations and comparison analysis |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T13%3A45%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=64-bit%20Block%20ciphers:%20hardware%20implementations%20and%20comparison%20analysis&rft.jtitle=Computers%20&%20electrical%20engineering&rft.au=Kitsos,%20P.&rft.date=2004-11-01&rft.volume=30&rft.issue=8&rft.spage=593&rft.epage=604&rft.pages=593-604&rft.issn=0045-7906&rft.eissn=1879-0755&rft_id=info:doi/10.1016/j.compeleceng.2004.11.001&rft_dat=%3Cproquest_cross%3E29114009%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c352t-61a0559e3b5053265deb9a5f918c05aac02846e17a698bf60644a5622d9820b93%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=29114009&rft_id=info:pmid/&rfr_iscdi=true |