Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression

Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level...

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Bibliographic Details
Published in:Computers & electrical engineering 2005-11, Vol.31 (8), p.572-588
Main Authors: Masoudnia, A., Sarbazi-Azad, H., Boussakta, S.
Format: Article
Language:English
Subjects:
Compression
Decompression
FPGA implementation
Image processing
Pipelining
Serial-parallel architecture
Wavelet transform
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Summary:Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4 × 4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time.
ISSN:0045-7906
1879-0755
DOI:10.1016/j.compeleceng.2005.07.005