Design techniques for high-speed multirate multistage FIR digital filters

• Published in: International journal of electronics 2006-10, Vol.93 (10), p.699-721
• Main Authors: Lin, M.-C., Chen, H.-Y., Jou, S.-J.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; FIR digital filter; Frequency filters; Interpolated FIR filter; Multirate
• ISSN: 0020-7217; 1362-3060
• DOI: 10.1080/00207210600810838

This paper presents architecture design techniques for implementing both single-rate and multirate high-speed finite impulse response (FIR) digital filters, with emphasis on the multirate multistage interpolated FIR (IFIR) digital filters. Well-known techniques to achieve high-speed and low-power applications for the single-rate digital FIR architecture are summarized, followed by the introduction of variable filter order selection, optimal filter decomposition, memory-saving and mirror symmetric filter pairs techniques which offer further gains in both performance and complexity reduction for the multirate multistage digital FIR architecture. A filter design example with TSMC 0.25 µm standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity application. Moreover, for high-speed application, the chip can operate at 714 MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach.