High-end server system partitioning for cost reduction

In this paper, we demonstrate the use of finite-dimension linear programming to maximize the number of partial good multicore processor chips in a symmetric multiprocessing (SMP) node of a given logical size and physical footprint. It is asserted that to the first order the cost of a productized pro...

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Bibliographic Details
Published in:IEEE transactions on advanced packaging 2006-02, Vol.29 (1), p.5-10
Main Authors: Katopis, G.A., Tingdong Zhou, Thornton, M.
Format: Article
Language:English
Subjects:
Applied sciences
Chip scale packaging
Chip yield
Chips
Cost engineering
Cost function
Cost reduction
Design optimization
Design. Technologies. Operation analysis. Testing
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Footprints
Hardware
Integrated circuits
Integrated circuits by function (including memories and processors)
Linear programming
Microprocessors
multicore chip technology
Multicore processing
Multiprocessing
Multiprocessing (computers)
Process design
Scrap
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
server system partitioning
Servers
Studies
system cost
Testing
Timing
Yield estimation
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Summary:In this paper, we demonstrate the use of finite-dimension linear programming to maximize the number of partial good multicore processor chips in a symmetric multiprocessing (SMP) node of a given logical size and physical footprint. It is asserted that to the first order the cost of a productized processor chip will be proportional to the scrap of a processor chip containing good cores but being unusable for the implementation of an SMP node. Therefore, the tradeoff between the number of processing units (PUs) on a chip and the total number of PUs on an SMP node is examined. This paper shows that an optimized SMP offering can be found so that the total chip cost of a high-end system can be minimized. However, such cost reduction will limit the SMP node size for a given processor chip yield. It will also be shown that as the chip yield improves the SMP node size that can be profitably implemented will increase.
ISSN:1521-3323
1557-9980
DOI:10.1109/TADVP.2005.862644