Low temperature crystallized Ta2O5/Nb2O5 bi-layers integrated into RIR capacitor for 60 nm generation and beyond

Ta2O5/Nb2O5 bi-layers were prepared on Ru/SiO2/Si substrate by Atomic Layer Deposition, and post annealed up to 575°C. The crystallization temperature of the bi-layers was 550°C, which was 100°C lower than that of Ta2O5 single layer. The thickness of the dielectric layers was also important paramete...

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Bibliographic Details
Published in:Microelectronic engineering 2005-06, Vol.80, p.317-320
Main Authors: Cho, Kyuho, Lee, Jinil, Lim, Jae-Soon, Lim, Hanjin, Lee, Junghyun, Park, Sungho, Yoo, Cha-Young, Kim, Sung-Tae, Chung, U-In, Moon, Joo-Tae
Format: Article
Language:English
Subjects:
Applied sciences
Dielectric, amorphous and glass solid devices
DRAM capacitor
Electronics
Exact sciences and technology
Materials
RIR
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Ta2O5/Nb2O5
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Summary:Ta2O5/Nb2O5 bi-layers were prepared on Ru/SiO2/Si substrate by Atomic Layer Deposition, and post annealed up to 575°C. The crystallization temperature of the bi-layers was 550°C, which was 100°C lower than that of Ta2O5 single layer. The thickness of the dielectric layers was also important parameter for the crystallization temperature. Transmittance Electron Microscopy image and depth profile analysis showed that Ta2O5 and Nb2O5 mixed each other during the crystallization. It was suggested that inter diffusion of two layers decreased the crystallization temperature of the bi-layers. Equivalent oxide thickness of crystalline Ru/Ta2O5/Nb2O5/Ru capacitor was 7.6Å with less than 100nA/cm2 leakage currents, which satisfied the requirements for 60nm generation DRAM capacitor and beyond.
ISSN:0167-9317
1873-5568
DOI:10.1016/j.mee.2005.04.032