A DUAL-GATE CELL (DGC) FeRAM WITH NDRO AND RANDOM ACCESS SCHEME FOR NANOSCALE AND TERABIT NON-VOLATILE MEMORY

This paper proposes a new dual-gate cell (DGC) FeRAM. The dual-gate cell is composed with MFSFET and MOSFET faced in parallel with common drain, source and float channel. The gates of the dual-gate cell are controlled by wordline and bottom wordline, respectively. A multitude of the dual-gate cells...

Full description

Saved in:
Bibliographic Details
Published in:Integrated ferroelectrics 2006-11, Vol.81 (1), p.141-148
Main Authors: KANG, HEE-BOK, LEE, JAE-JIN, HONG, SUK-KYOUNG, AHN, JIN-HONG, KIH, JOONG-SIK, SUNG, MAN YOUNG, SUNG, YOUNG-KWON
Format: Article
Language:English
Subjects:
depletion DGC
dual-gate cell (DGC) FeRAM
enhancement DGC
MFSFET
non-destructive read out (NDRO)
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites cdi_FETCH-LOGICAL-c329t-d87046d8a290b642f13b024b216646391ac53601efa9d0c051cce93af7dfc64e3
container_end_page 148
container_issue 1
container_start_page 141
container_title Integrated ferroelectrics
container_volume 81
creator KANG, HEE-BOK
LEE, JAE-JIN
HONG, SUK-KYOUNG
AHN, JIN-HONG
KIH, JOONG-SIK
SUNG, MAN YOUNG
SUNG, YOUNG-KWON
description This paper proposes a new dual-gate cell (DGC) FeRAM. The dual-gate cell is composed with MFSFET and MOSFET faced in parallel with common drain, source and float channel. The gates of the dual-gate cell are controlled by wordline and bottom wordline, respectively. A multitude of the dual-gate cells are arrayed in serial connection for unit array scheme. The WL_1 to WL_m of MFSFET are not biased for sensing operation in read mode, thus there are no degradation and disturbance to the cell retention data in read access. The write cycle composed with two sub-write cycles of data '1' preserve or data '0' write cycle after the first sub-write cycle of data '1' write to all active cells. The data '1' is preserved by the same voltage polarity between WL_1 and channel voltage of the MFSFET. The random access operation is possible in both read and write mode with non-destructive read out (NDRO).
doi_str_mv 10.1080/10584580600660249
format article
fullrecord <record><control><sourceid>proquest_infor</sourceid><recordid>TN_cdi_proquest_miscellaneous_29377397</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>29377397</sourcerecordid><originalsourceid>FETCH-LOGICAL-c329t-d87046d8a290b642f13b024b216646391ac53601efa9d0c051cce93af7dfc64e3</originalsourceid><addsrcrecordid>eNqFkE1r3DAQhk1oIWmSH9CbTiE5uBlZtmRBLopX-wH-AK-T0pPRyjJs8K5TyUubfx81m1sIvcwMvO8zw7xB8B3DDwwp3GJI0jhJgQJQClHMT4IzTIGFaZzyL372eugN7DT45twTACYJo2fBTqDZg8jDhWgkymSeo-vZIrtBc1OLAv1cNUtUzuoKiXKGal-qAoksk-s1WmdLWUg0r2pUirJaZyKXb7ZG1uJ-1aCyKsPHKhfNyguFLKr610XwtVeDM5fv_Tx4mMsmW4Z5tVj5BaEmEZ_CLmUQ0y5VEYcNjaMek43_aRNhSmNKOFY6IRSw6RXvQEOCtTacqJ51vaaxIefB1XHvsx1_H4yb2t3WaTMMam_Gg2sjThgjnHkjPhq1HZ2zpm-f7Xan7EuLof0XbPshWM-wI7Pd96PdqT-jHbp2Ui_DaHur9nrrPlLt9Hfy5N1_SfL54VeBZIV4</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>29377397</pqid></control><display><type>article</type><title>A DUAL-GATE CELL (DGC) FeRAM WITH NDRO AND RANDOM ACCESS SCHEME FOR NANOSCALE AND TERABIT NON-VOLATILE MEMORY</title><source>Taylor and Francis Science and Technology Collection</source><creator>KANG, HEE-BOK ; LEE, JAE-JIN ; HONG, SUK-KYOUNG ; AHN, JIN-HONG ; KIH, JOONG-SIK ; SUNG, MAN YOUNG ; SUNG, YOUNG-KWON</creator><creatorcontrib>KANG, HEE-BOK ; LEE, JAE-JIN ; HONG, SUK-KYOUNG ; AHN, JIN-HONG ; KIH, JOONG-SIK ; SUNG, MAN YOUNG ; SUNG, YOUNG-KWON</creatorcontrib><description>This paper proposes a new dual-gate cell (DGC) FeRAM. The dual-gate cell is composed with MFSFET and MOSFET faced in parallel with common drain, source and float channel. The gates of the dual-gate cell are controlled by wordline and bottom wordline, respectively. A multitude of the dual-gate cells are arrayed in serial connection for unit array scheme. The WL_1 to WL_m of MFSFET are not biased for sensing operation in read mode, thus there are no degradation and disturbance to the cell retention data in read access. The write cycle composed with two sub-write cycles of data '1' preserve or data '0' write cycle after the first sub-write cycle of data '1' write to all active cells. The data '1' is preserved by the same voltage polarity between WL_1 and channel voltage of the MFSFET. The random access operation is possible in both read and write mode with non-destructive read out (NDRO).</description><identifier>ISSN: 1058-4587</identifier><identifier>EISSN: 1607-8489</identifier><identifier>DOI: 10.1080/10584580600660249</identifier><language>eng</language><publisher>Taylor &amp; Francis Group</publisher><subject>depletion DGC ; dual-gate cell (DGC) FeRAM ; enhancement DGC ; MFSFET ; non-destructive read out (NDRO)</subject><ispartof>Integrated ferroelectrics, 2006-11, Vol.81 (1), p.141-148</ispartof><rights>Copyright Taylor &amp; Francis Group, LLC 2006</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c329t-d87046d8a290b642f13b024b216646391ac53601efa9d0c051cce93af7dfc64e3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids></links><search><creatorcontrib>KANG, HEE-BOK</creatorcontrib><creatorcontrib>LEE, JAE-JIN</creatorcontrib><creatorcontrib>HONG, SUK-KYOUNG</creatorcontrib><creatorcontrib>AHN, JIN-HONG</creatorcontrib><creatorcontrib>KIH, JOONG-SIK</creatorcontrib><creatorcontrib>SUNG, MAN YOUNG</creatorcontrib><creatorcontrib>SUNG, YOUNG-KWON</creatorcontrib><title>A DUAL-GATE CELL (DGC) FeRAM WITH NDRO AND RANDOM ACCESS SCHEME FOR NANOSCALE AND TERABIT NON-VOLATILE MEMORY</title><title>Integrated ferroelectrics</title><description>This paper proposes a new dual-gate cell (DGC) FeRAM. The dual-gate cell is composed with MFSFET and MOSFET faced in parallel with common drain, source and float channel. The gates of the dual-gate cell are controlled by wordline and bottom wordline, respectively. A multitude of the dual-gate cells are arrayed in serial connection for unit array scheme. The WL_1 to WL_m of MFSFET are not biased for sensing operation in read mode, thus there are no degradation and disturbance to the cell retention data in read access. The write cycle composed with two sub-write cycles of data '1' preserve or data '0' write cycle after the first sub-write cycle of data '1' write to all active cells. The data '1' is preserved by the same voltage polarity between WL_1 and channel voltage of the MFSFET. The random access operation is possible in both read and write mode with non-destructive read out (NDRO).</description><subject>depletion DGC</subject><subject>dual-gate cell (DGC) FeRAM</subject><subject>enhancement DGC</subject><subject>MFSFET</subject><subject>non-destructive read out (NDRO)</subject><issn>1058-4587</issn><issn>1607-8489</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><recordid>eNqFkE1r3DAQhk1oIWmSH9CbTiE5uBlZtmRBLopX-wH-AK-T0pPRyjJs8K5TyUubfx81m1sIvcwMvO8zw7xB8B3DDwwp3GJI0jhJgQJQClHMT4IzTIGFaZzyL372eugN7DT45twTACYJo2fBTqDZg8jDhWgkymSeo-vZIrtBc1OLAv1cNUtUzuoKiXKGal-qAoksk-s1WmdLWUg0r2pUirJaZyKXb7ZG1uJ-1aCyKsPHKhfNyguFLKr610XwtVeDM5fv_Tx4mMsmW4Z5tVj5BaEmEZ_CLmUQ0y5VEYcNjaMek43_aRNhSmNKOFY6IRSw6RXvQEOCtTacqJ51vaaxIefB1XHvsx1_H4yb2t3WaTMMam_Gg2sjThgjnHkjPhq1HZ2zpm-f7Xan7EuLof0XbPshWM-wI7Pd96PdqT-jHbp2Ui_DaHur9nrrPlLt9Hfy5N1_SfL54VeBZIV4</recordid><startdate>20061101</startdate><enddate>20061101</enddate><creator>KANG, HEE-BOK</creator><creator>LEE, JAE-JIN</creator><creator>HONG, SUK-KYOUNG</creator><creator>AHN, JIN-HONG</creator><creator>KIH, JOONG-SIK</creator><creator>SUNG, MAN YOUNG</creator><creator>SUNG, YOUNG-KWON</creator><general>Taylor &amp; Francis Group</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7QQ</scope><scope>7SP</scope><scope>7SR</scope><scope>8FD</scope><scope>JG9</scope><scope>L7M</scope></search><sort><creationdate>20061101</creationdate><title>A DUAL-GATE CELL (DGC) FeRAM WITH NDRO AND RANDOM ACCESS SCHEME FOR NANOSCALE AND TERABIT NON-VOLATILE MEMORY</title><author>KANG, HEE-BOK ; LEE, JAE-JIN ; HONG, SUK-KYOUNG ; AHN, JIN-HONG ; KIH, JOONG-SIK ; SUNG, MAN YOUNG ; SUNG, YOUNG-KWON</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c329t-d87046d8a290b642f13b024b216646391ac53601efa9d0c051cce93af7dfc64e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2006</creationdate><topic>depletion DGC</topic><topic>dual-gate cell (DGC) FeRAM</topic><topic>enhancement DGC</topic><topic>MFSFET</topic><topic>non-destructive read out (NDRO)</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>KANG, HEE-BOK</creatorcontrib><creatorcontrib>LEE, JAE-JIN</creatorcontrib><creatorcontrib>HONG, SUK-KYOUNG</creatorcontrib><creatorcontrib>AHN, JIN-HONG</creatorcontrib><creatorcontrib>KIH, JOONG-SIK</creatorcontrib><creatorcontrib>SUNG, MAN YOUNG</creatorcontrib><creatorcontrib>SUNG, YOUNG-KWON</creatorcontrib><collection>CrossRef</collection><collection>Ceramic Abstracts</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>Technology Research Database</collection><collection>Materials Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Integrated ferroelectrics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>KANG, HEE-BOK</au><au>LEE, JAE-JIN</au><au>HONG, SUK-KYOUNG</au><au>AHN, JIN-HONG</au><au>KIH, JOONG-SIK</au><au>SUNG, MAN YOUNG</au><au>SUNG, YOUNG-KWON</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A DUAL-GATE CELL (DGC) FeRAM WITH NDRO AND RANDOM ACCESS SCHEME FOR NANOSCALE AND TERABIT NON-VOLATILE MEMORY</atitle><jtitle>Integrated ferroelectrics</jtitle><date>2006-11-01</date><risdate>2006</risdate><volume>81</volume><issue>1</issue><spage>141</spage><epage>148</epage><pages>141-148</pages><issn>1058-4587</issn><eissn>1607-8489</eissn><abstract>This paper proposes a new dual-gate cell (DGC) FeRAM. The dual-gate cell is composed with MFSFET and MOSFET faced in parallel with common drain, source and float channel. The gates of the dual-gate cell are controlled by wordline and bottom wordline, respectively. A multitude of the dual-gate cells are arrayed in serial connection for unit array scheme. The WL_1 to WL_m of MFSFET are not biased for sensing operation in read mode, thus there are no degradation and disturbance to the cell retention data in read access. The write cycle composed with two sub-write cycles of data '1' preserve or data '0' write cycle after the first sub-write cycle of data '1' write to all active cells. The data '1' is preserved by the same voltage polarity between WL_1 and channel voltage of the MFSFET. The random access operation is possible in both read and write mode with non-destructive read out (NDRO).</abstract><pub>Taylor &amp; Francis Group</pub><doi>10.1080/10584580600660249</doi><tpages>8</tpages></addata></record>
fulltext fulltext
identifier ISSN: 1058-4587
ispartof Integrated ferroelectrics, 2006-11, Vol.81 (1), p.141-148
issn 1058-4587
1607-8489
language eng
recordid cdi_proquest_miscellaneous_29377397
source Taylor and Francis Science and Technology Collection
subjects depletion DGC
dual-gate cell (DGC) FeRAM
enhancement DGC
MFSFET
non-destructive read out (NDRO)
title A DUAL-GATE CELL (DGC) FeRAM WITH NDRO AND RANDOM ACCESS SCHEME FOR NANOSCALE AND TERABIT NON-VOLATILE MEMORY
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T19%3A02%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_infor&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20DUAL-GATE%20CELL%20(DGC)%20FeRAM%20WITH%20NDRO%20AND%20RANDOM%20ACCESS%20SCHEME%20FOR%20NANOSCALE%20AND%20TERABIT%20NON-VOLATILE%20MEMORY&rft.jtitle=Integrated%20ferroelectrics&rft.au=KANG,%20HEE-BOK&rft.date=2006-11-01&rft.volume=81&rft.issue=1&rft.spage=141&rft.epage=148&rft.pages=141-148&rft.issn=1058-4587&rft.eissn=1607-8489&rft_id=info:doi/10.1080/10584580600660249&rft_dat=%3Cproquest_infor%3E29377397%3C/proquest_infor%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c329t-d87046d8a290b642f13b024b216646391ac53601efa9d0c051cce93af7dfc64e3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=29377397&rft_id=info:pmid/&rfr_iscdi=true