Integrating firewire peripheral interface with an ethernet custom network processor

• Published in: Integration (Amsterdam) 2007-07, Vol.40 (4), p.536-548
• Main Authors: Elkeelany, O., Chaudhry, G.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Hardware description language; Integrated circuits; Integrated circuits by function (including memories and processors); Low-power design; Network ready devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Simulation; Synthesis
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2006.09.003

Bandwidth demands on ubiquitous Ethernet have grown immensely, driven by the rapid expansion of real-time applications like audio/video streaming. In a related research, the authors designed a novel high-performance custom network processor chip using field programmable gate arrays (FPGAs). The main function of this chip (named SPEED) is to bypass the operating system processing of network protocol stack at the host computer by off-loading its networking functions to hardware. This simplification is not only required to fit in a hardware solution, but also it improves network performance. The novel chip utilizes the concept of Ethernet channels, where Ethernet frames are addressed in a multicast addressing scheme. In this article, we integrate the chip with a Firewire peripheral interface (FPI). A crucial function of the FPI design is to convert the IEEE 1394 isochronous traffic to the Ethernet frame format via two independent asynchronous write and read buffers. The FPI also manages the SPEED hardware interrupt signals in a bi-directional communication scheme. The goal of this research is to map isochronous Firewire packets into Ethernet frames by utilizing the SPEED Ethernet channel assignment capability. We used Verilog Hardware Description Language (HDL) to synthesize the FPI design. Since the FPI needs to support bi-directional communication, we also present a generic HDL model for bi-directional data sharing, which can be used in similar bi-directional applications. Initial performance measures show that the FPI consumes less that 0.15 W of power. Also we found that the synthesized design utilizes only 28% of the target chip resources. Hence it was possible to incorporate it with the SPEED design in the same FPGA chip. This low power consumption will lead to powering SPEED-FPI based network devices through the network cable and eliminate the process of regular electrical power outlet installations and maintenance. Thus, the SPEED-FPI system reduces the installation complexity, especially for large number of devices (e.g., surveillance cameras).