Development of dual-etch via tapering process for through-silicon interconnection

• Published in: Sensors and actuators. A. Physical. 2007-09, Vol.139 (1), p.323-329
• Main Authors: Nagarajan, Ranganathan, Prasad, Krishnamachar, Ebin, Liao, Narayanan, Balasubramanian
• Format: Article
• Language: English
• Subjects: 3D system in packaging; BOSCH process; Dual-etch; Tapered silicon via; Through-silicon interconnection
• ISSN: 0924-4247; 1873-3069
• DOI: 10.1016/j.sna.2007.01.014

A novel dual-etch process technology has been developed for the tapering of deep silicon vias which can be used in the fabrication of through-silicon interconnected silicon carriers for 3D system in packaging application. The process consists of two etching steps viz. an anisotropic etch process followed by a global isotropic etch process which causes the vias profile to taper. The 1st etching step is designed to provide high etch rate and throughput while the 2nd etch step is designed to control the taper angle of the via. It has been shown that through this approach of partitioning the via formation process into an anisotropic etch and an isotropic etch process, it is possible to maintain high overall etch rates without compromising on the final via profile and throughput. The via profile achieved has been extensively characterized with respect wide range of critical process parameters and via geometries. It has been demonstrated that regardless of the choice of via formation method, it is feasible to achieve a controllable via taper to realize a void-free copper via-filling by electroplating process.