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Advanced Hi-Fill ® for interconnect liner applications

Ti/TiN liner and barrier deposition for low contact resistance tungsten plug interconnect metallisation schemes represent a major challenge for current and future aspect ratios of interconnect vias. For Ti, bottom coverage is important to minimise contact and via resistance and for TiN, good sidewal...

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Published in:Microelectronic engineering 2002-10, Vol.64 (1), p.99-105
Main Authors: Urbansky, N, Burgess, S.R, Schmidbauer, S, Heydenreich, U, Donohue, H, Moncrieff, I, Görgens, C
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container_issue 1
container_start_page 99
container_title Microelectronic engineering
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creator Urbansky, N
Burgess, S.R
Schmidbauer, S
Heydenreich, U
Donohue, H
Moncrieff, I
Görgens, C
description Ti/TiN liner and barrier deposition for low contact resistance tungsten plug interconnect metallisation schemes represent a major challenge for current and future aspect ratios of interconnect vias. For Ti, bottom coverage is important to minimise contact and via resistance and for TiN, good sidewall coverage is required to maintain the integrity of the W fill process. This paper describes the fundamental operation and characterisation of a novel ionised dual metal/metal nitride deposition chamber—Advanced Hi-Fill ®. Discussed is the incorporation of Advanced Hi-Fill ® technology into a BEOL production environment. Production data for via level interconnects manufactured in a 0.17-μm logic product as well as contact level for a 0.14-μm DRAM product is presented.
doi_str_mv 10.1016/S0167-9317(02)00787-6
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fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_30255337</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S0167931702007876</els_id><sourcerecordid>30255337</sourcerecordid><originalsourceid>FETCH-LOGICAL-c316t-aa88108667392d53e504228e5727860dd268f08dad3a16709ca8259cada0dc33</originalsourceid><addsrcrecordid>eNqFkMtKAzEUQIMoWKufIMxG0UX0Jmkes5JSrAoFF3YfQpKBSDozJtOCP-VH-GWmD3Tp5l4unPs6CF0SuCNAxP1bCRLXjMgboLcAUkksjtCIKMkw50Ido9EvcorOcn6HUk9AjZCcuo1prXfVc8DzEGP1_VU1XapCO_hku7b1dqhiaH2qTN_HYM0Qujafo5PGxOwvDnmMlvPH5ewZL16fXmbTBbaMiAEboxQBJYRkNXWceQ4TSpXnkkolwDkqVAPKGcdMuRBqaxTlJToDzjI2Rtf7sX3qPtY-D3oVsvUxmtZ366wZUM4ZkwXke9CmLufkG92nsDLpUxPQW0t6Z0lvFWigemdJi9J3dVhgsjWxSUVGyH_NrGZcUF64hz3ny7Ob4JPONvituJCKIe268M-mH8LQesQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>30255337</pqid></control><display><type>article</type><title>Advanced Hi-Fill ® for interconnect liner applications</title><source>Elsevier</source><creator>Urbansky, N ; Burgess, S.R ; Schmidbauer, S ; Heydenreich, U ; Donohue, H ; Moncrieff, I ; Görgens, C</creator><creatorcontrib>Urbansky, N ; Burgess, S.R ; Schmidbauer, S ; Heydenreich, U ; Donohue, H ; Moncrieff, I ; Görgens, C</creatorcontrib><description>Ti/TiN liner and barrier deposition for low contact resistance tungsten plug interconnect metallisation schemes represent a major challenge for current and future aspect ratios of interconnect vias. For Ti, bottom coverage is important to minimise contact and via resistance and for TiN, good sidewall coverage is required to maintain the integrity of the W fill process. This paper describes the fundamental operation and characterisation of a novel ionised dual metal/metal nitride deposition chamber—Advanced Hi-Fill ®. Discussed is the incorporation of Advanced Hi-Fill ® technology into a BEOL production environment. Production data for via level interconnects manufactured in a 0.17-μm logic product as well as contact level for a 0.14-μm DRAM product is presented.</description><identifier>ISSN: 0167-9317</identifier><identifier>EISSN: 1873-5568</identifier><identifier>DOI: 10.1016/S0167-9317(02)00787-6</identifier><identifier>CODEN: MIENEF</identifier><language>eng</language><publisher>Amsterdam: Elsevier B.V</publisher><subject>Applied sciences ; Deposition process ; Diffusion barrier ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Exact sciences and technology ; Interconnect liner ; Ti/TiN</subject><ispartof>Microelectronic engineering, 2002-10, Vol.64 (1), p.99-105</ispartof><rights>2002 Elsevier Science B.V.</rights><rights>2002 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>309,310,314,780,784,789,790,23930,23931,25140,27924,27925</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&amp;idt=13935625$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Urbansky, N</creatorcontrib><creatorcontrib>Burgess, S.R</creatorcontrib><creatorcontrib>Schmidbauer, S</creatorcontrib><creatorcontrib>Heydenreich, U</creatorcontrib><creatorcontrib>Donohue, H</creatorcontrib><creatorcontrib>Moncrieff, I</creatorcontrib><creatorcontrib>Görgens, C</creatorcontrib><title>Advanced Hi-Fill ® for interconnect liner applications</title><title>Microelectronic engineering</title><description>Ti/TiN liner and barrier deposition for low contact resistance tungsten plug interconnect metallisation schemes represent a major challenge for current and future aspect ratios of interconnect vias. For Ti, bottom coverage is important to minimise contact and via resistance and for TiN, good sidewall coverage is required to maintain the integrity of the W fill process. This paper describes the fundamental operation and characterisation of a novel ionised dual metal/metal nitride deposition chamber—Advanced Hi-Fill ®. Discussed is the incorporation of Advanced Hi-Fill ® technology into a BEOL production environment. Production data for via level interconnects manufactured in a 0.17-μm logic product as well as contact level for a 0.14-μm DRAM product is presented.</description><subject>Applied sciences</subject><subject>Deposition process</subject><subject>Diffusion barrier</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Interconnect liner</subject><subject>Ti/TiN</subject><issn>0167-9317</issn><issn>1873-5568</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><recordid>eNqFkMtKAzEUQIMoWKufIMxG0UX0Jmkes5JSrAoFF3YfQpKBSDozJtOCP-VH-GWmD3Tp5l4unPs6CF0SuCNAxP1bCRLXjMgboLcAUkksjtCIKMkw50Ido9EvcorOcn6HUk9AjZCcuo1prXfVc8DzEGP1_VU1XapCO_hku7b1dqhiaH2qTN_HYM0Qujafo5PGxOwvDnmMlvPH5ewZL16fXmbTBbaMiAEboxQBJYRkNXWceQ4TSpXnkkolwDkqVAPKGcdMuRBqaxTlJToDzjI2Rtf7sX3qPtY-D3oVsvUxmtZ366wZUM4ZkwXke9CmLufkG92nsDLpUxPQW0t6Z0lvFWigemdJi9J3dVhgsjWxSUVGyH_NrGZcUF64hz3ny7Ob4JPONvituJCKIe268M-mH8LQesQ</recordid><startdate>20021001</startdate><enddate>20021001</enddate><creator>Urbansky, N</creator><creator>Burgess, S.R</creator><creator>Schmidbauer, S</creator><creator>Heydenreich, U</creator><creator>Donohue, H</creator><creator>Moncrieff, I</creator><creator>Görgens, C</creator><general>Elsevier B.V</general><general>Elsevier Science</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20021001</creationdate><title>Advanced Hi-Fill ® for interconnect liner applications</title><author>Urbansky, N ; Burgess, S.R ; Schmidbauer, S ; Heydenreich, U ; Donohue, H ; Moncrieff, I ; Görgens, C</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c316t-aa88108667392d53e504228e5727860dd268f08dad3a16709ca8259cada0dc33</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Applied sciences</topic><topic>Deposition process</topic><topic>Diffusion barrier</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Interconnect liner</topic><topic>Ti/TiN</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Urbansky, N</creatorcontrib><creatorcontrib>Burgess, S.R</creatorcontrib><creatorcontrib>Schmidbauer, S</creatorcontrib><creatorcontrib>Heydenreich, U</creatorcontrib><creatorcontrib>Donohue, H</creatorcontrib><creatorcontrib>Moncrieff, I</creatorcontrib><creatorcontrib>Görgens, C</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Microelectronic engineering</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Urbansky, N</au><au>Burgess, S.R</au><au>Schmidbauer, S</au><au>Heydenreich, U</au><au>Donohue, H</au><au>Moncrieff, I</au><au>Görgens, C</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Advanced Hi-Fill ® for interconnect liner applications</atitle><jtitle>Microelectronic engineering</jtitle><date>2002-10-01</date><risdate>2002</risdate><volume>64</volume><issue>1</issue><spage>99</spage><epage>105</epage><pages>99-105</pages><issn>0167-9317</issn><eissn>1873-5568</eissn><coden>MIENEF</coden><abstract>Ti/TiN liner and barrier deposition for low contact resistance tungsten plug interconnect metallisation schemes represent a major challenge for current and future aspect ratios of interconnect vias. For Ti, bottom coverage is important to minimise contact and via resistance and for TiN, good sidewall coverage is required to maintain the integrity of the W fill process. This paper describes the fundamental operation and characterisation of a novel ionised dual metal/metal nitride deposition chamber—Advanced Hi-Fill ®. Discussed is the incorporation of Advanced Hi-Fill ® technology into a BEOL production environment. Production data for via level interconnects manufactured in a 0.17-μm logic product as well as contact level for a 0.14-μm DRAM product is presented.</abstract><cop>Amsterdam</cop><pub>Elsevier B.V</pub><doi>10.1016/S0167-9317(02)00787-6</doi><tpages>7</tpages></addata></record>
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ispartof Microelectronic engineering, 2002-10, Vol.64 (1), p.99-105
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1873-5568
language eng
recordid cdi_proquest_miscellaneous_30255337
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subjects Applied sciences
Deposition process
Diffusion barrier
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Interconnect liner
Ti/TiN
title Advanced Hi-Fill ® for interconnect liner applications
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T20%3A07%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Advanced%20Hi-Fill%20%C2%AE%20for%20interconnect%20liner%20applications&rft.jtitle=Microelectronic%20engineering&rft.au=Urbansky,%20N&rft.date=2002-10-01&rft.volume=64&rft.issue=1&rft.spage=99&rft.epage=105&rft.pages=99-105&rft.issn=0167-9317&rft.eissn=1873-5568&rft.coden=MIENEF&rft_id=info:doi/10.1016/S0167-9317(02)00787-6&rft_dat=%3Cproquest_cross%3E30255337%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c316t-aa88108667392d53e504228e5727860dd268f08dad3a16709ca8259cada0dc33%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=30255337&rft_id=info:pmid/&rfr_iscdi=true