ASIP architecture exploration for efficient IPSec encryption: A case study

• Published in: ACM transactions on embedded computing systems 2007-05, Vol.6 (2), p.12
• Main Authors: Scharwaechter, Hanno, Kammler, David, Wieferink, Andreas, Hohenauer, Manuel, Karuri, Kingshuk, Ceng, Jianjiang, Leupers, Rainer, Ascheid, Gerd, Meyr, Heinrich
• Format: Article
• Language: English
• ISSN: 1539-9087; 1558-3465
• DOI: 10.1145/1234675.1234679

Application-Specific Instruction-Set Processors (ASIPs) are becoming increasingly popular in the world of customized, application-driven System-on-Chip (SoC) designs. Efficient ASIP design requires an iterative architecture exploration loop---gradual refinement of the processor architecture starting from an initial template. To accomplish this task, design automation tools are used to detect bottlenecks in embedded applications, to implement application-specific processor instructions, and to automatically generate the required software tools (such as instruction-set simulator, C-compiler, assembler, and profiler), as well as to synthesize the hardware. This paper describes an architecture exploration loop for an ASIP coprocessor that implements common encryption functionality used in symmetric block cipher algorithms for internet protocol security (IPSec). The coprocessor is accessed via shared memory and, as a consequence, our approach is easily adaptable to arbitrary main processor architectures. This paper presents the extended version of our case study that has been already published on the SCOPES conference in 2004. In both papers, a MIPS architecture is used as the main processor and Blowfish as encryption algorithm.