A 1.0ns 64-bits GaAs Adder using Quad tree algorithm

This paper describes a full custom 64.bits adder targeting the VITESSE E/D MESFET process HGaAsIII. This adder which respects a bit slice topology is part of the project of GaAs data-path compiler for ALLIANCE CAD TOOLS. GaAs's specific properties have been exploited in a full custom approach....

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Bibliographic Details
Main Authors: Royannez, Philippe, Amara, Amara
Format: Conference Proceeding
Language:English
Online Access:Get full text
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Summary:This paper describes a full custom 64.bits adder targeting the VITESSE E/D MESFET process HGaAsIII. This adder which respects a bit slice topology is part of the project of GaAs data-path compiler for ALLIANCE CAD TOOLS. GaAs's specific properties have been exploited in a full custom approach. Original architecture have been used to increase the parallelism of carries' computation. The layout is portable using a symbolic approach and could also be used with other E/D MESFET process.
DOI:10.1109/GLSV.1996.497587