Behavioral characterization of multiprocessor memory systems: a case study

• Main Authors: Gallivan, K., Gannon, D., Jalby, W., Malony, A., Wijshoff, H.
• Format: Conference Proceeding
• Language: English
• Subjects: Computer systems organization > Architectures > Distributed architectures > Grid computing; Computer systems organization > Architectures > Parallel architectures > Multicore architectures; Computer systems organization > Architectures > Parallel architectures > Systolic arrays; Computer systems organization > Architectures > Serial architectures > Superscalar architectures; Computing methodologies > Modeling and simulation > Simulation types and techniques > Massively parallel and high-performance simulations; General and reference > Cross-computing tools and techniques > Performance; Software and its engineering > Software notations and tools; Software and its engineering > Software notations and tools > General programming languages > Language types; Software and its engineering > Software organization and properties > Contextual software domains > Operating systems > Memory management > Main memory; Software and its engineering > Software organization and properties > Software system structures > Distributed systems organizing principles > Grid computing
• ISSN: 0163-5999
• DOI: 10.1145/75108.75381

The speed and efficiency of the memory system is a key limiting factor in the performance of supercomputers. Consequently, one of the major concerns when developing a high-performance code, either manually or automatically, is determining and characterizing the influence of the memory system on performance in terms of algorithmic parameters. Unfortunately, the performance data available to an algorithm designer such as various benchmarks and, occasionally, manufacturer-supplied information, e.g. instruction timings and architecture component characteristics, are rarely sufficient for this task. In this paper, we discuss a systematic methodology for probing the performance characteristics of a memory system via a hierarchy of data-movement kernels. We present and analyze the results obtained by such a methodology on a cache-based multi-vector processor (Alliant FX/8). Finally, we indicate how these experimental results can be used for predicting the performance of simple Fortran codes by a combination of empirical observations, architectural models and analytical techniques.