A CMOS VLSI Implementation of an NxN Multiplexing Circuitry for ATM Applications

A non internal blocking ATM packet switching network using CMOS technology has been developed for an NxN switch. A multiplexing circuitry with 32 inputs was designed and implemented using simple logic gates. The development has utilized an interconnection network of 1x32 parallel expander circuits....

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Bibliographic Details
Main Author: Aldridge, Richard L
Format: Conference Proceeding
Language:English
Online Access:Get full text
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Summary:A non internal blocking ATM packet switching network using CMOS technology has been developed for an NxN switch. A multiplexing circuitry with 32 inputs was designed and implemented using simple logic gates. The development has utilized an interconnection network of 1x32 parallel expander circuits. The control unit consisting of serial shift registers and latches to keep the destination path open for the length of the packet, were designed using MAGIC software and simulated by IFWM. As low as 5ns delay was estimated by the 1x32 expander circuit, while the clock generated by the combinational circuit for latching showed a delay of 190ns. The system has been fabricated using MOSIS services, and as minimum of 5ns delay was measured between the input and output nodes of the switchingcircuit.
DOI:10.1109/GLSV.1996.497629