Design and optimization of low voltage high performance dual threshold CMOS circuits

Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transi...

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Bibliographic Details
Main Authors: Wei, Liqiong, Chen, Zhanping, Johnson, Mark, Roy, Kaushik, De, Vivek
Format: Conference Proceeding
Language:English
Subjects:
Applied computing > Physical sciences and engineering > Engineering
Computer systems organization > Dependable and fault-tolerant systems and networks
General and reference > Cross-computing tools and techniques > Performance
Hardware > Integrated circuits > Semiconductor memory
Hardware > Robustness
Mathematics of computing > Mathematical software
Networks > Network performance evaluation
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Summary:Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by IISPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.
ISSN:0738-100X
DOI:10.1145/277044.277179