Folding of logic functions and its application to look up table compaction

• Main Authors: Kimura, Shinji, Horiyama, Takashi, Nakanishi, Masaki, Kajihara, Hirotsugu
• Format: Conference Proceeding
• Language: English
• Subjects: Applied sciences; Circuit properties; Computing methodologies > Symbolic and algebraic manipulation > Symbolic and algebraic algorithms; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Hardware > Electronic design automation > High-level and register-transfer level synthesis; Hardware > Integrated circuits > Semiconductor memory; Hardware > Very large scale integration design > Application-specific VLSI designs; Integrated circuits; Integrated circuits by function (including memories and processors); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Theory of computation > Design and analysis of algorithms
• ISSN: 1092-3152
• DOI: 10.1145/774572.774674

The paper describes the folding method of logic functions to reduce the size of memories for keeping the functions. The folding is based on the relation of fractions of logic functions. We show that the fractions of the full adder function have the bit-wise NOT relation and the bit-wise OR relation, and that the memory size becomes half (8-bit). We propose a new 3--1 LUT with the folding mechanisms whcih can implement a full adder with one LUT. A fast carry propagation line is introduced for a multi-bit addition. The folding and fast carry propagation mechanisms are shown to be useful to implement other multi-bit operations and general 4 input functions without extra hardware resources. The paper shows the reduction of the area consumption when using our LUTs compared to the case using 4--1 LUTs on several benchmark circuits.