An automatic testbench generation tool for a SystemC functional verification methodology

The advent of new 90nm/130nm VLSI technology and SoC design methodologies, has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any design flow. New methods are required that allow for easier, quicker...

Full description

Saved in:
Bibliographic Details
Main Authors: da Silva, Karina R. G., Melcher, Elmar U. K., Araujo, Guido, Pimenta, Valdiney Alves
Format: Conference Proceeding
Language:English
Subjects:
Automatic testing
Circuit testing
Design methodology
Digital audio players
Explosives
Hardware > Hardware test
Hardware > Robustness > Hardware reliability
Hardware design languages
Libraries
Permission
System testing
Very large scale integration
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The advent of new 90nm/130nm VLSI technology and SoC design methodologies, has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any design flow. New methods are required that allow for easier, quicker and more reusable verification. In this paper we propose an automatic verification methodology approach that enables fast, transaction-level, coverage-driven, self-checking and random-constraint functional verification. Our approach uses the SystemC Verification Library (SCV), to synthesize a tool capable of automatically generating testbench templates. A case study from a real MP3 design is used to show the effectiveness of our approach.
DOI:10.1145/1016568.1016592