SystemC: a modeling platform supporting multiple design abstractions

• Main Author: Panda, Preeti Ranjan
• Format: Conference Proceeding
• Language: English
• Subjects: Computer systems organization; Computer systems organization > Embedded and cyber-physical systems; Computer systems organization > Real-time systems; Computing methodologies > Modeling and simulation > Model development and analysis; Computing methodologies > Modeling and simulation > Model development and analysis > Modeling methodologies; Design automation; Design methodology; Embedded software; Hardware > Communication hardware, interfaces and storage > Signal processing systems; Hardware > Electronic design automation > Hardware description languages and compilation; Hardware > Electronic design automation > High-level and register-transfer level synthesis; Hardware > Hardware validation > Functional verification; Hardware > Hardware validation > Functional verification > Simulation and emulation; Hardware design languages; Integrated circuit synthesis; Kernel; Software and its engineering > Software notations and tools > System description languages; Software libraries; Standardization; System testing; System-level design
• DOI: 10.1145/500001.500018

SystemC is a C++ based modeling platform supporting design abstractions at the register-transfer, behavioral, and system levels. Consisting of a class library and a simulation kernel, the language is an attempt at standardization of a C/C++ design methodology, and is supported by the Open SystemC Initiative (OSCI), a consortium of a wide range of system houses, semiconductor companies, Intellectual property (IP) providers, embedded software developers, and design automation tool vendors. The advantages of SystemC include the establishment of a common design environment consisting of C++ libraries, models and tools, thereby setting up a foundation for hardware-software co-design; the ability to exchange IP easily and efficiently; and the ability to reuse test benches across different levels of modeling abstraction. We outline the features of SystemC that make it an attractive language for design specification, verification, and synthesis at different levels of abstraction, with particular emphasis on the new features included in SystemC 2.0 that support system-level design.