The effect of register-transfer design tradeoffs on chip area and performance

• Main Authors: Granacki, John J., Parker, Alice C.
• Format: Conference Proceeding
• Language: English
• Subjects: Hardware > Electronic design automation > High-level and register-transfer level synthesis > Datapath optimization; Hardware > Electronic design automation > Physical design (EDA) > Placement; Hardware > Electronic design automation > Physical design (EDA) > Wire routing; Hardware > Emerging technologies; Hardware > Hardware validation; Hardware > Very large scale integration design; Theory of computation > Computational complexity and cryptography; Theory of computation > Computational complexity and cryptography > Complexity classes
• DOI: 10.5555/800032.800701

This paper describes an experiment to determine how register-transfer tradeoffs affect the resultant silicon area and performance of layouts. Six register-transfer level designs, each performing the same function with different register transfer level structures, were implemented using a library of CMOS/SOS standard cells, and an automatic placement and routing program. The consumption of area and the critical path timing were calculated for each design. The results show that register-transfer design variations do produce changes in area and performance at the layout level. However, optimistic timing analysis at the RT level, variations in relative storage timing across technologies, and omission of fanout and path length delays altered the resultant area and timing from that predicted at the RT level.