A fast-lock delay-locked loop architecture with improved precharged PFD

In this paper, a dual charge pump architecture for fast-lock delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock DLL uses only one phase frequency detector (PFD) to perform dual path tuning and a lock control circuit to control the switching between the two path. An improved PFD...

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Bibliographic Details
Published in:Analog integrated circuits and signal processing 2008-05, Vol.55 (2), p.149-154
Main Authors: Lip-Kai, Soh, Sulaiman, Mohd-Shahiman, Yusoff, Zubaida
Format: Article
Language:English
Subjects:
Circuits and Systems
Electrical Engineering
Engineering
Signal,Image and Speech Processing
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Summary:In this paper, a dual charge pump architecture for fast-lock delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock DLL uses only one phase frequency detector (PFD) to perform dual path tuning and a lock control circuit to control the switching between the two path. An improved PFD is proposed to reduce the output jitter by reducing the one-shot pulse produced when the reference signal and feedback signal is in phase. The proposed DLL circuit is designed based on the Silterra 0.18-μm 1P6M CMOS process with a 1.8-V supply voltage. The active area of the proposed DLL circuit is 327.46 × 116.16 μm. An experimental chip was implemented and measured. The measurement results show that the proposed DLL has fast locking properties.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-008-9131-7