Phaser: Phased methodology for modeling the system-level effects of soft errors

This paper presents an overview of Phaser, a toolset and methodology for modeling the effects of soft errors on the architectural and microarchitectural functionality of a system. The Phaser framework is used to understand the system-level effects of soft-error rates of a microprocessor chip as its...

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Bibliographic Details
Published in:IBM journal of research and development 2008-05, Vol.52 (3), p.293-306
Main Authors: Rivers, J A, Bose, P, Kudva, P, Wellman, J-D, Sanda, P N, Cannon, E H, Alves, L C
Format: Article
Language:English
Subjects:
High performance systems
Microprocessors
Semiconductors
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Summary:This paper presents an overview of Phaser, a toolset and methodology for modeling the effects of soft errors on the architectural and microarchitectural functionality of a system. The Phaser framework is used to understand the system-level effects of soft-error rates of a microprocessor chip as its design evolves through the phases of preconcept, concept, high-level design, and register-transfer-level design implementation. Phaser represents a strategic research vision that is being proposed as a next-generation toolset for predicting chip-level failure rates and studying reliability-performance tradeoffs during the phased design process. This paper primarily presents Phaser/M1, the early stage of the predictive modeling of behavior. [PUBLICATION ABSTRACT]
ISSN:0018-8646
0018-8646
2151-8556
DOI:10.1147/rd.523.0293