A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU

Supporting both WCDMA with HSDPA and GSM/GPRS/EDGE, the 9.3 times 9.3 mm 2 SoC fabricated in triple-Vth 65 nm CMOS, has three CPU cores and 20 separate power domains. Unused power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music pla...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2009-01, Vol.44 (1), p.83-89
Main Authors: Ito, M., Nitta, K., Ohno, K., Saigusa, M., Nishida, M., Yoshioka, S., Irita, T., Koike, T., Kamei, T., Komuro, T., Hattori, T., Arai, Y., Kodama, Y.
Format: Article
Language:English
Subjects:
Activation
Application processor
Applied sciences
Automatic voltage control
Baseband
baseband processor
cellular phone
Circuit properties
Circuits
Circuits of signal characteristics conditioning (including delay circuits)
clock activation
Clocks
CMOS
Decoding
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Energy consumption
Exact sciences and technology
Frames per second
Ground penetrating radar
GSM
Integrated circuits
Integrated circuits by function (including memories and processors)
Layout
memory space
MPEG encoders
Multiaccess communication
Phase locked loops
Power consumption
power domains
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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Description
Summary:Supporting both WCDMA with HSDPA and GSM/GPRS/EDGE, the 9.3 times 9.3 mm 2 SoC fabricated in triple-Vth 65 nm CMOS, has three CPU cores and 20 separate power domains. Unused power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music playback scene dynamically stops a PLL and clock trees when not necessary and reduces power consumption from 33.6 mW to 19.6 mW. IP-MMU translates virtual address to physical address for 18 hardware-IPs and virtual address space can be allocated when necessary and can be freed after its operation, reducing external memory by 43 MB. Video performance of D1 (720 times 520) size with 30 frames per second for MPEG/AVC decoding and encoding can be achieved under mixed virtual and physical address usage.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2008.2007169