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A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage
In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge 2 -Sb 2 -TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To...
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Published in: | IEEE journal of solid-state circuits 2009-01, Vol.44 (1), p.217-227 |
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creator | Bedeschi, F. Fackenthal, R. Resta, C. Donze, E.M. Jagasivamani, M. Buda, E.C. Pellizzer, F. Chow, D.W. Cabrini, A. Calvi, G. Faravelli, R. Fantini, A. Torelli, G. Mills, D. Gastaldi, R. Casagrande, G. |
description | In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge 2 -Sb 2 -TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure. |
doi_str_mv | 10.1109/JSSC.2008.2006439 |
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Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2008.2006439</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuits ; Current distribution ; Current measurement ; Cycles ; Design. Technologies. Operation analysis. Testing ; Durability ; Electrical resistance measurement ; Electronics ; Endurance ; Exact sciences and technology ; Feasibility ; Germanium alloys ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Magnetic and optical mass memories ; Nonvolatile memory ; Phase change ; Phase change materials ; Phase change memory ; Phase measurement ; Placing ; Programming ; Semiconductor device measurement ; Semiconductor electronics. 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Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.</description><subject>Applied sciences</subject><subject>Circuits</subject><subject>Current distribution</subject><subject>Current measurement</subject><subject>Cycles</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Durability</subject><subject>Electrical resistance measurement</subject><subject>Electronics</subject><subject>Endurance</subject><subject>Exact sciences and technology</subject><subject>Feasibility</subject><subject>Germanium alloys</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Magnetic and optical mass memories</subject><subject>Nonvolatile memory</subject><subject>Phase change</subject><subject>Phase change materials</subject><subject>Phase change memory</subject><subject>Phase measurement</subject><subject>Placing</subject><subject>Programming</subject><subject>Semiconductor device measurement</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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subjects | Applied sciences Circuits Current distribution Current measurement Cycles Design. Technologies. Operation analysis. Testing Durability Electrical resistance measurement Electronics Endurance Exact sciences and technology Feasibility Germanium alloys Integrated circuits Integrated circuits by function (including memories and processors) Magnetic and optical mass memories Nonvolatile memory Phase change Phase change materials Phase change memory Phase measurement Placing Programming Semiconductor device measurement Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Storage and reproduction of information Testing |
title | A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage |
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