Loading…

A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage

In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge 2 -Sb 2 -TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 2009-01, Vol.44 (1), p.217-227
Main Authors: Bedeschi, F., Fackenthal, R., Resta, C., Donze, E.M., Jagasivamani, M., Buda, E.C., Pellizzer, F., Chow, D.W., Cabrini, A., Calvi, G., Faravelli, R., Fantini, A., Torelli, G., Mills, D., Gastaldi, R., Casagrande, G.
Format: Article
Language:English
Subjects:
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by cdi_FETCH-LOGICAL-c531t-d38fade9d99a51a7ed385a0c8732a1e011434abc7c1bfe83c860552ce623459e3
cites cdi_FETCH-LOGICAL-c531t-d38fade9d99a51a7ed385a0c8732a1e011434abc7c1bfe83c860552ce623459e3
container_end_page 227
container_issue 1
container_start_page 217
container_title IEEE journal of solid-state circuits
container_volume 44
creator Bedeschi, F.
Fackenthal, R.
Resta, C.
Donze, E.M.
Jagasivamani, M.
Buda, E.C.
Pellizzer, F.
Chow, D.W.
Cabrini, A.
Calvi, G.
Faravelli, R.
Fantini, A.
Torelli, G.
Mills, D.
Gastaldi, R.
Casagrande, G.
description In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge 2 -Sb 2 -TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.
doi_str_mv 10.1109/JSSC.2008.2006439
format article
fullrecord <record><control><sourceid>proquest_pasca</sourceid><recordid>TN_cdi_proquest_miscellaneous_34414883</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4735567</ieee_id><sourcerecordid>903625325</sourcerecordid><originalsourceid>FETCH-LOGICAL-c531t-d38fade9d99a51a7ed385a0c8732a1e011434abc7c1bfe83c860552ce623459e3</originalsourceid><addsrcrecordid>eNqFkdFLHDEQxkOp0Kv6B5S-LIXWp9XMJtkkj3bRVjlROIW-hTE3e67s7Z7JruB_b7Z3-NCHCkOGyfy-j4SPsS_AjwG4PblcLKrjgnMzHaUU9gObgVImBy3-fGQzzsHkNu0-sc8xPqZRSgMzdnGa_Ww2fYshX1BLfqBldvOAkbLqAbsVZVe07sNLdk44jKHpVtnV2A5NPqdnarOK2jZbDH3AFR2wvRrbSIe7vs_uzs9uq9_5_PrXRXU6z70SMORLYWpckl1aiwpQU7pQyL3RokAgDiCFxHuvPdzXZIQ3JVeq8FQWQipLYp8dbX03oX8aKQ5u3USfHoId9WN0louyUCLVe6TRihdS64n88V9SSAnSGJHAb_-Aj_0YuvRfZwGstWAnCLaQD32MgWq3Cc0aw4sD7qa03JSWm9Jyu7SS5vvOGKPHtg7Y-Sa-CQtI7uqv99ct1xDR21pqoVSpxSsDBZr4</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>911999193</pqid></control><display><type>article</type><title>A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage</title><source>IEEE Xplore (Online service)</source><creator>Bedeschi, F. ; Fackenthal, R. ; Resta, C. ; Donze, E.M. ; Jagasivamani, M. ; Buda, E.C. ; Pellizzer, F. ; Chow, D.W. ; Cabrini, A. ; Calvi, G. ; Faravelli, R. ; Fantini, A. ; Torelli, G. ; Mills, D. ; Gastaldi, R. ; Casagrande, G.</creator><creatorcontrib>Bedeschi, F. ; Fackenthal, R. ; Resta, C. ; Donze, E.M. ; Jagasivamani, M. ; Buda, E.C. ; Pellizzer, F. ; Chow, D.W. ; Cabrini, A. ; Calvi, G. ; Faravelli, R. ; Fantini, A. ; Torelli, G. ; Mills, D. ; Gastaldi, R. ; Casagrande, G.</creatorcontrib><description>In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge 2 -Sb 2 -TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2008.2006439</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuits ; Current distribution ; Current measurement ; Cycles ; Design. Technologies. Operation analysis. Testing ; Durability ; Electrical resistance measurement ; Electronics ; Endurance ; Exact sciences and technology ; Feasibility ; Germanium alloys ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Magnetic and optical mass memories ; Nonvolatile memory ; Phase change ; Phase change materials ; Phase change memory ; Phase measurement ; Placing ; Programming ; Semiconductor device measurement ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Storage and reproduction of information ; Testing</subject><ispartof>IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.217-227</ispartof><rights>2009 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c531t-d38fade9d99a51a7ed385a0c8732a1e011434abc7c1bfe83c860552ce623459e3</citedby><cites>FETCH-LOGICAL-c531t-d38fade9d99a51a7ed385a0c8732a1e011434abc7c1bfe83c860552ce623459e3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4735567$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,780,784,789,790,4050,4051,23930,23931,25140,27924,27925,54796</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&amp;idt=21119593$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Bedeschi, F.</creatorcontrib><creatorcontrib>Fackenthal, R.</creatorcontrib><creatorcontrib>Resta, C.</creatorcontrib><creatorcontrib>Donze, E.M.</creatorcontrib><creatorcontrib>Jagasivamani, M.</creatorcontrib><creatorcontrib>Buda, E.C.</creatorcontrib><creatorcontrib>Pellizzer, F.</creatorcontrib><creatorcontrib>Chow, D.W.</creatorcontrib><creatorcontrib>Cabrini, A.</creatorcontrib><creatorcontrib>Calvi, G.</creatorcontrib><creatorcontrib>Faravelli, R.</creatorcontrib><creatorcontrib>Fantini, A.</creatorcontrib><creatorcontrib>Torelli, G.</creatorcontrib><creatorcontrib>Mills, D.</creatorcontrib><creatorcontrib>Gastaldi, R.</creatorcontrib><creatorcontrib>Casagrande, G.</creatorcontrib><title>A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge 2 -Sb 2 -TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.</description><subject>Applied sciences</subject><subject>Circuits</subject><subject>Current distribution</subject><subject>Current measurement</subject><subject>Cycles</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Durability</subject><subject>Electrical resistance measurement</subject><subject>Electronics</subject><subject>Endurance</subject><subject>Exact sciences and technology</subject><subject>Feasibility</subject><subject>Germanium alloys</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Magnetic and optical mass memories</subject><subject>Nonvolatile memory</subject><subject>Phase change</subject><subject>Phase change materials</subject><subject>Phase change memory</subject><subject>Phase measurement</subject><subject>Placing</subject><subject>Programming</subject><subject>Semiconductor device measurement</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Storage and reproduction of information</subject><subject>Testing</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><recordid>eNqFkdFLHDEQxkOp0Kv6B5S-LIXWp9XMJtkkj3bRVjlROIW-hTE3e67s7Z7JruB_b7Z3-NCHCkOGyfy-j4SPsS_AjwG4PblcLKrjgnMzHaUU9gObgVImBy3-fGQzzsHkNu0-sc8xPqZRSgMzdnGa_Ww2fYshX1BLfqBldvOAkbLqAbsVZVe07sNLdk44jKHpVtnV2A5NPqdnarOK2jZbDH3AFR2wvRrbSIe7vs_uzs9uq9_5_PrXRXU6z70SMORLYWpckl1aiwpQU7pQyL3RokAgDiCFxHuvPdzXZIQ3JVeq8FQWQipLYp8dbX03oX8aKQ5u3USfHoId9WN0louyUCLVe6TRihdS64n88V9SSAnSGJHAb_-Aj_0YuvRfZwGstWAnCLaQD32MgWq3Cc0aw4sD7qa03JSWm9Jyu7SS5vvOGKPHtg7Y-Sa-CQtI7uqv99ct1xDR21pqoVSpxSsDBZr4</recordid><startdate>200901</startdate><enddate>200901</enddate><creator>Bedeschi, F.</creator><creator>Fackenthal, R.</creator><creator>Resta, C.</creator><creator>Donze, E.M.</creator><creator>Jagasivamani, M.</creator><creator>Buda, E.C.</creator><creator>Pellizzer, F.</creator><creator>Chow, D.W.</creator><creator>Cabrini, A.</creator><creator>Calvi, G.</creator><creator>Faravelli, R.</creator><creator>Fantini, A.</creator><creator>Torelli, G.</creator><creator>Mills, D.</creator><creator>Gastaldi, R.</creator><creator>Casagrande, G.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>200901</creationdate><title>A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage</title><author>Bedeschi, F. ; Fackenthal, R. ; Resta, C. ; Donze, E.M. ; Jagasivamani, M. ; Buda, E.C. ; Pellizzer, F. ; Chow, D.W. ; Cabrini, A. ; Calvi, G. ; Faravelli, R. ; Fantini, A. ; Torelli, G. ; Mills, D. ; Gastaldi, R. ; Casagrande, G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c531t-d38fade9d99a51a7ed385a0c8732a1e011434abc7c1bfe83c860552ce623459e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Applied sciences</topic><topic>Circuits</topic><topic>Current distribution</topic><topic>Current measurement</topic><topic>Cycles</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Durability</topic><topic>Electrical resistance measurement</topic><topic>Electronics</topic><topic>Endurance</topic><topic>Exact sciences and technology</topic><topic>Feasibility</topic><topic>Germanium alloys</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Magnetic and optical mass memories</topic><topic>Nonvolatile memory</topic><topic>Phase change</topic><topic>Phase change materials</topic><topic>Phase change memory</topic><topic>Phase measurement</topic><topic>Placing</topic><topic>Programming</topic><topic>Semiconductor device measurement</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Storage and reproduction of information</topic><topic>Testing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Bedeschi, F.</creatorcontrib><creatorcontrib>Fackenthal, R.</creatorcontrib><creatorcontrib>Resta, C.</creatorcontrib><creatorcontrib>Donze, E.M.</creatorcontrib><creatorcontrib>Jagasivamani, M.</creatorcontrib><creatorcontrib>Buda, E.C.</creatorcontrib><creatorcontrib>Pellizzer, F.</creatorcontrib><creatorcontrib>Chow, D.W.</creatorcontrib><creatorcontrib>Cabrini, A.</creatorcontrib><creatorcontrib>Calvi, G.</creatorcontrib><creatorcontrib>Faravelli, R.</creatorcontrib><creatorcontrib>Fantini, A.</creatorcontrib><creatorcontrib>Torelli, G.</creatorcontrib><creatorcontrib>Mills, D.</creatorcontrib><creatorcontrib>Gastaldi, R.</creatorcontrib><creatorcontrib>Casagrande, G.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Xplore (Online service)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology &amp; Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Bedeschi, F.</au><au>Fackenthal, R.</au><au>Resta, C.</au><au>Donze, E.M.</au><au>Jagasivamani, M.</au><au>Buda, E.C.</au><au>Pellizzer, F.</au><au>Chow, D.W.</au><au>Cabrini, A.</au><au>Calvi, G.</au><au>Faravelli, R.</au><au>Fantini, A.</au><au>Torelli, G.</au><au>Mills, D.</au><au>Gastaldi, R.</au><au>Casagrande, G.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2009-01</date><risdate>2009</risdate><volume>44</volume><issue>1</issue><spage>217</spage><epage>227</epage><pages>217-227</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change Ge 2 -Sb 2 -TeB alloy is presented. Memory cells are bipolar selected, and are based on a /xtrench architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distribu tions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 degC bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same mutrench cell structure.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/JSSC.2008.2006439</doi><tpages>11</tpages></addata></record>
fulltext fulltext
identifier ISSN: 0018-9200
ispartof IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.217-227
issn 0018-9200
1558-173X
language eng
recordid cdi_proquest_miscellaneous_34414883
source IEEE Xplore (Online service)
subjects Applied sciences
Circuits
Current distribution
Current measurement
Cycles
Design. Technologies. Operation analysis. Testing
Durability
Electrical resistance measurement
Electronics
Endurance
Exact sciences and technology
Feasibility
Germanium alloys
Integrated circuits
Integrated circuits by function (including memories and processors)
Magnetic and optical mass memories
Nonvolatile memory
Phase change
Phase change materials
Phase change memory
Phase measurement
Placing
Programming
Semiconductor device measurement
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Storage and reproduction of information
Testing
title A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T12%3A08%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_pasca&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Bipolar-Selected%20Phase%20Change%20Memory%20Featuring%20Multi-Level%20Cell%20Storage&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Bedeschi,%20F.&rft.date=2009-01&rft.volume=44&rft.issue=1&rft.spage=217&rft.epage=227&rft.pages=217-227&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2008.2006439&rft_dat=%3Cproquest_pasca%3E903625325%3C/proquest_pasca%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c531t-d38fade9d99a51a7ed385a0c8732a1e011434abc7c1bfe83c860552ce623459e3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=911999193&rft_id=info:pmid/&rft_ieee_id=4735567&rfr_iscdi=true