Analysis and Design of a CMOS Phase-Tunable Injection-Coupled LC Quadrature VCO (PTIC-QVCO)

This paper presents the design, analysis, and characterization of a low-power, low-phase-noise, phase-tunable injection-coupled LC quadrature oscillator (PTIC-QVCO). Two LC VCOs are superharmonically coupled in quadrature phase via a frequency doubler that injects a synchronizing signal at the commo...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2009-03, Vol.44 (3), p.784-796
Main Authors: Chamas, I.R., Raman, S.
Format: Article
Language:English
Subjects:
Analytical models
Applied sciences
Circuit properties
Circuits
CMOS
Coupling circuits
Cross-coupled differential oscillator
Design engineering
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Filters
Frequency filters
Frequency synchronization
image rejection
injection locking
Integrated circuits
Mathematical models
Noise
Noise measurement
Oscillators
Oscillators, resonators, synthetizers
Phase noise
quadrature phase generation
Quadratures
RF CMOS
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Studies
superharmonic coupling
Tail
Transconductors
Tunable circuits and devices
Tuning
Voltage-controlled oscillators
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Summary:This paper presents the design, analysis, and characterization of a low-power, low-phase-noise, phase-tunable injection-coupled LC quadrature oscillator (PTIC-QVCO). Two LC VCOs are superharmonically coupled in quadrature phase via a frequency doubler that injects a synchronizing signal at the common source node of the negative transconductor stage. Conceptual and analytical models of the circuit are introduced to derive the conditions for quadrature operation and examine the circuit parameters affecting the phase imbalance due to mismatched VCOs. Additionally, a tunable tail filter (TTF) is incorporated to calibrate the residual quadrature imbalance in presence of a 3-sigma variation in the device parameters and drive the oscillator to its optimum phase noise performance. To validate the proposed approach, measurements have been carried out on a 9 GHz prototype implemented in a 0.18 mum RF CMOS process. With core current consumption of 5 mA at 1.8 V supply voltage, the circuit achieves a measured phase noise figure-of-merit ranging from 177.3 to 182.6 dBc/Hz at 3 MHz offset along the 9.0 to 9.6 GHz frequency tuning range. Quadrature phase correction of plusmn11 0 at 9 GHz is demonstrated.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2008.2011976