Reducing Area Overhead for Error-Protecting Large L2/L3 Caches

• Published in: IEEE transactions on computers 2009-03, Vol.58 (3), p.300-310
• Main Author: Kim, Soontae
• Format: Article
• Language: English
• Subjects: Architecture; Arrays; Benchmarks; Cache memories; Cleaning; Computer architecture; Error correction codes; Error-checking; Errors; Parity check codes; Processors; Program processors; Reliability; Running; Soft errors; SRAM; Studies; System-on-a-chip
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2008.174

Due to increasing concern about various errors, current processors adopt error protection mechanisms for their on-chip components. Especially, protecting caches in current processors incurs as much as 12.5 percent area overhead due to error-correcting codes (ECCs). Considering large L2/L3 caches employed in current high-performance processors, the area overhead is very high, consuming a large number of on-chip transistors. As an attempt to reduce that overhead, this paper proposes an area-efficient error protection architecture for large L2/L3 caches. First, it selectively applies ECC to only dirty cache lines, and other clean cache lines are protected by using simple parity check codes. Second, the dirty cache lines are periodically cleaned by exploiting the generational behavior of cache lines in order not to increase traffic to the off-chip main memory. Experimental results show that the cleaning technique effectively reduces the average number of dirty cache lines per cycle. The ECCs of the reduced dirty cache lines can be confined in a small ECC array or ECC cache. Our proposed error protection architecture has been shown to reduce the area overhead of a 1-Mbyte L2 cache for error protection by 59 percent with less than 1 percent performance degradation, on the average, using SPEC2000 benchmarks running on a typical four-issue superscalar processor. A dirty cache line cleaning scheme is also beneficial for reducing the vulnerability of tag arrays to soft errors.