SRAM Cell Stability: A Dynamic Perspective

SRAM cell stability assessment is traditionally based on static criteria of data stability requiring three coincident points in DC butterfly curves. This definition is based on static (DC) characteristics of the cell transistors. We introduce the dynamic criteria of cell data stability knowing that...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2009-02, Vol.44 (2), p.609-619
Main Authors: Sharifkhani, M., Sachdev, M.
Format: Article
Language:English
Subjects:
Access time
Applied sciences
Assessments
Circuit noise
Circuit stability
Circuit testing
CMOS technology
Criteria
Data stability
Design. Technologies. Operation analysis. Testing
Direct current
dynamic data stability
Dynamics
Electronics
Exact sciences and technology
Feedback circuits
Integrated circuits
Integrated circuits by function (including memories and processors)
Inverters
Noise
non-linear circuit
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
SRAM
SRAM cell
Stability
Stability criteria
Static random access memory
Transistors
Voltage
Working environment noise
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Summary:SRAM cell stability assessment is traditionally based on static criteria of data stability requiring three coincident points in DC butterfly curves. This definition is based on static (DC) characteristics of the cell transistors. We introduce the dynamic criteria of cell data stability knowing that the cell operates in a dynamic environment alternating between access and non-access conditions. The proposed definition of the dynamic data stability criteria introduces a new bound for the cell static noise margin (SNM). It reveals that the true noise margin of the cell can be made considerably higher than the conventional SNM once the cell access time is sufficiently shorter than the cell time-constant. This phenomena can be used to extend the noise margin in (partial) subthreshold SRAMs. Moreover, a simulation method for verification of the dynamic data stability criteria is presented. Silicon measurement results in 130 nm CMOS technology confirms the concept of dynamic data stability and designer's ability to trade timing and static parameters . Finally, it is shown that the long time constant due to the subthreshold operation of the cell can be exploited to maintain data stability with proper choice of access and recovery time.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2008.2010818