Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic

Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2007-12, Vol.54 (6), p.2060-2064
Main Authors: Amusan, O.A., Massengill, L.W., Bhuva, B.L., DasGupta, S., Witulski, A.F., Ahlbin, J.R.
Format: Article
Language:English
Subjects:
Amplification
Bipolar transistors
Charge
Charge collection
charge confinement
CMOS
CMOS logic circuits
CMOS technology
Collection
Contact
Design engineering
Design optimization
lateral parasitic bipolar
Logic
Logic design
Logic devices
MOS devices
n-well collapse
n-well contact area
n-well contact location
Pulse measurements
Pulse width
radiation hardened by design
Radiation hardening
Space vector pulse width modulation
transistor sizing
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Summary:Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2007.907754