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Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM
Two classes of techniques have been developed to whiten the quantization noise in digital delta-sigma modulators (DDSMs): deterministic and stochastic. In this two-part paper, a design methodology for reduced-complexity DDSMs is presented. The design methodology is based on error masking. Rules for...
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Published in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2009-04, Vol.56 (4), p.714-726 |
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container_title | IEEE transactions on circuits and systems. I, Regular papers |
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creator | Zhipeng Ye Kennedy, M.P. |
description | Two classes of techniques have been developed to whiten the quantization noise in digital delta-sigma modulators (DDSMs): deterministic and stochastic. In this two-part paper, a design methodology for reduced-complexity DDSMs is presented. The design methodology is based on error masking. Rules for selecting the word lengths of the stages in multistage architectures are presented. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation and experimental results confirm theoretical predictions. Part I addresses MultistAge noise SHaping (MASH) DDSMs; Part II focuses on single-quantizer DDSMs. |
doi_str_mv | 10.1109/TCSI.2008.2003383 |
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source | IEEE Xplore (Online service) |
subjects | Delta modulation Delta-sigma modulation Design engineering Design methodology Digital Digital delta-sigma modulators (DDSMs) Digital modulation error masking Errors Feedback loop Hardware Masking Modulators Multi-stage noise shaping Multistage MultistAge noise SHaping (MASH) Noise Quantization Semiconductor device noise Stochastic resonance |
title | Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part I: MASH DDSM |
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