A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

Most existing power gating structures provide only one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate power-saving and data-retaining mode. Experiments with test structures fabricated in 0.13-mum CMOS bulk technology show that our po...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2007-07, Vol.54 (7), p.586-590
Main Authors: Suhwan Kim, Kosonocky, S.V., Knebel, D.R., Stawiasz, K., Papaefthymiou, M.C.
Format: Article
Language:English
Subjects:
Circuits
CMOS
CMOS technology
Deep-submicrometer CMOS
Design engineering
Gating and risering
ground bounce noise
Leakage current
Logic circuits
Low voltage
MOS devices
MOSFETs
multi-threshold CMOS (MTCMOS)
Power dissipation
Space technology
Supports
System-on-a-chip
Threshold voltage
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Description
Summary:Most existing power gating structures provide only one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate power-saving and data-retaining mode. Experiments with test structures fabricated in 0.13-mum CMOS bulk technology show that our power gating structure yields an expanded design space with more power-performance tradeoff alternatives.
ISSN:1549-7747
1057-7130
1558-3791
DOI:10.1109/TCSII.2007.894428