Plasma etching of HfO@@d2@ in metal gate CMOS devices

• Published in: Microelectronic engineering 2009-04, Vol.86 (4-6), p.965-967
• Main Authors: Sungauer, E, Mellhaoui, X, Pargon, E, Joubert, O
• Format: Article
• Language: English
• ISSN: 0167-9317
• DOI: 10.1016/j.mee.2008.10.026

With the introduction of new materials in the CMOS gate stacks, such as metal and high-@@ik@ materials, plasma etching has to address new challenges. The authors present a study dedicated to the etching of thin HfO@@d2@ layers in BCl@@d3@ plasmas. This etching process must be selective with respect to Si and SiO@@d2@ since the underlying silicon substrate must not be damaged. In this work, it is shown that HfO@@d2@ etching with infinite selectivity can be achieved by adjusting the bias power in pure BCl@@d3@ plasma, by diluting BCl@@d3@ in argon, and by conditioning the reactor walls with a carbon coating before BCl@@d3@ process. However, the etch process has to minimize the deposition rate of boron polymers on silicon surfaces in order to prevent the formation of HfO@@d2@ residues. The anisotropic profile of the gate is maintained during the BCl@@d3@ plasma step. The c-Si surface presents no contamination (Hf or B) after HfO@@d2@ etching process and wet post-treatment. Reactor wall cleaning issues are also addressed.