Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses

This paper purposes a bus architecture called skewed repeater bus (SRB) for reducing on-chip interconnect energy in microprocessors. By introducing a dynamic relative delay between neighboring bus lines, SRB reduces both average and worst-case coupling capacitance between those lines. SRB is compare...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2008-08, Vol.55 (7), p.1904-1910
Main Authors: Ghoneima, M.M., Khellah, M.M., Tschanz, J., Yibin Ye, Kurd, N., Barkatullah, J.S., Nimmagadda, S., Ismail, Y., De, V.K.
Format: Article
Language:English
Subjects:
Buses (vehicles)
Capacitance
Capacitors
Circuits
Clocks
Coupling capacitance
Coupling circuits
Delay
Dynamical systems
Dynamics
Energy dissipation
Integrated circuit interconnections
interconnects
low-power design
Microprocessors
on-chip bus
repeater
Repeaters
Simulation
Switches
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Summary:This paper purposes a bus architecture called skewed repeater bus (SRB) for reducing on-chip interconnect energy in microprocessors. By introducing a dynamic relative delay between neighboring bus lines, SRB reduces both average and worst-case coupling capacitance between those lines. SRB is compared to previously published techniques like delayed data bus (DDB) and delayed clock bus (DCB). Simulation results in 65-nm process show that bus energy reduction of 18% is achieved when SRB is applied to a real microprocessor example, versus 11% and 7% only for DDB and DCB, respectively.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2008.928527