A Speed-Optimized Systolic Array Processor Architecture for Spatio-Temporal 2-D IIR Broadband Beam Filters

• Published in: IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2008-08, Vol.55 (7), p.1953-1966
• Main Authors: Arjuna Madanayake, H.L.P., Bruton, L.T.
• Format: Article
• Language: English
• Subjects: 2-D; Architecture; array; beam; Beams (radiation); Broadband; Circuits; Delay; digital; digital signal processing (DSP); Field programmable gate arrays; field-programmable gate array (FPGA); filter; Filtering; Frequency; High speed; IIR filters; infinite-impulse response (IIR); Integrated circuits; Microprocessors; Pipelines; plane wave; sensors; systolic; Systolic arrays; Timing; Very large scale integration; VLSI
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2008.918214

For high-speed plane-wave filtering applications, real-time 2-D spatio-temporal linear-array broadband beam filters are required, operating at temporal frame rates in excess of hundreds of megahertz. The corresponding application specific VLSI circuits must have low critical-path latencies. A novel high-speed systolic array architecture for a first-order 2-D broadband frequency-planar spatio-temporal beam filter is proposed for this purpose and employs a field-programmable gate array (FPGA) circuit where the critical path latency is minimized by timing optimization of inter- and intra-parallel processor pipelines, together with 3-D look-ahead techniques. The method facilitates single-chip VLSI circuit implementations operating at real-time frame rates of several hundred megahertz.