A Disruptive Receiver Architecture Dedicated to Software-Defined Radio

The next generation of mobile terminals is faced with the emergence of the software-defined radio (SDR) concept. The communication devices tend to provide various wireless services through a multi-functional, multi-mode and multi-standard terminal. The SDR concept aims at designing a re-configurable...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. 2, Analog and digital signal processing Analog and digital signal processing, 2008-04, Vol.55 (4), p.344-348
Main Authors: Rivet, F., Deval, Y., Begueret, J.-B., Dallet, D., Cathelin, P., Belot, D.
Format: Article
Language:English
Subjects:
Analog signal processing
Analog-digital conversion
Architecture
Circuits
CMOS technology
cognitive radio
Devices
Digital
Digital signal processors
Electronics
Energy consumption
Engineering Sciences
Fast Fourier transforms
Fourier transforms
Mobile communication
Radio
Radio frequencies
Radio frequency
Receivers
sampled analog signal processor
Signal resolution
software-defined radio (SDR)
Terminals
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Summary:The next generation of mobile terminals is faced with the emergence of the software-defined radio (SDR) concept. The communication devices tend to provide various wireless services through a multi-functional, multi-mode and multi-standard terminal. The SDR concept aims at designing a re-configurable radio architecture accepting all cellular or noncellular standards working in the 0-5-GHz frequency range. Some technical challenges have to be solved in order to address this concept. Working in the digital domain may be a solution but the analog-to-digital conversion cannot be done at Radio Frequencies, at an acceptable resolution and at an acceptable level of power consumption. The idea proposed here was to interface an analog pre-processing circuit between the antenna and a digital signal processor to pre-condition the RF signal. It uses the principle of a fast Fourier transform to carry out basic functions with high accuracy in a low-cost technology like CMOS. This paper presents the design and the behavioral simulations of this analog discrete-time device which gives the hardware flexibility required for a cognitive radio component.
ISSN:1549-7747
1057-7130
1558-3791
DOI:10.1109/TCSII.2008.919512