Hardware Implementation for a Genetic Algorithm

A genetic algorithm (GA) can find an optimal solution in many complex problems. GAs have been widely used in many applications. A flexible-very-large-scale integration intellectual property for the GA has been proposed in this paper. This algorithm can dynamically perform various population sizes, f...

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Bibliographic Details
Published in:IEEE transactions on instrumentation and measurement 2008-04, Vol.57 (4), p.699-705
Main Authors: Pei-Yin Chen, Ren-Der Chen, Yu-Pin Chang, Leang-San Shieh, Malki, H.A.
Format: Article
Language:English
Subjects:
Application software
Clocks
Computer science
Computer simulation
Costs
Design automation
Field-programmable gate array (FPGA)
Fitness
genetic algorithm (GA)
Genetic algorithms
Genetic mutations
Hardware
Hardware design languages
Instrumentation
Intellectual property
intellectual property (IP)
Optimization
Running
software system
Software systems
Verilog
Very large scale integration
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Description
Summary:A genetic algorithm (GA) can find an optimal solution in many complex problems. GAs have been widely used in many applications. A flexible-very-large-scale integration intellectual property for the GA has been proposed in this paper. This algorithm can dynamically perform various population sizes, fitness lengths, individual lengths, fitness functions, crossover operations, and mutation-rate settings to meet the real-time requirements of various GA applications. It can be seen from the simulation results that our design works very well for the three examples running at an 83-MHz clock frequency.
ISSN:0018-9456
1557-9662
DOI:10.1109/TIM.2007.913807