High-bandwidth Address Generation Unit

In this paper we present an efficient data fetch circuitry to retrieve several operands from a n -way parallel memory system in a single machine cycle. The proposed address generation unit operates with an improved version of the low-order parallel memory access approach. Our design supports data st...

Full description

Saved in:
Bibliographic Details
Published in:Journal of signal processing systems 2009-10, Vol.57 (1), p.33-44
Main Authors: Galuzzi, Carlo, Gou, Chunyang, Calderón, Humberto, Gaydadjiev, Georgi N., Vassiliadis, Stamatis
Format: Article
Language:English
Subjects:
Circuits and Systems
Computer Imaging
Electrical Engineering
Engineering
Image Processing and Computer Vision
Pattern Recognition
Pattern Recognition and Graphics
Signal,Image and Speech Processing
Vision
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper we present an efficient data fetch circuitry to retrieve several operands from a n -way parallel memory system in a single machine cycle. The proposed address generation unit operates with an improved version of the low-order parallel memory access approach. Our design supports data structures of arbitrary lengths and different odd strides. The experimental results show that our address generation unit is capable of generating eight 32 −  bit addresses every 6 ns for different strides when implemented on a VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using only trivial hardware resources.
ISSN:1939-8018
1939-8115
DOI:10.1007/s11265-008-0174-x