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Pipelined Architecture for Additive Range Reduction
Range reduction is a crucial step for the accuracy in trigonometric functions evaluation. A new pipelined architecture to deal with range reduction for floating point representation is presented in this paper. The algorithm is based on a look-up table storing the corresponding powers of 2 mod A . Th...
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Published in: | Journal of signal processing systems 2008-11, Vol.53 (1-2), p.103-112 |
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Main Authors: | , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | Range reduction is a crucial step for the accuracy in trigonometric functions evaluation. A new pipelined architecture to deal with range reduction for floating point representation is presented in this paper. The algorithm is based on a look-up table storing the corresponding powers of 2 mod
A
. The overall design has been optimized for a modulo equal to 2
π
, which is the most widely used due to trigonometric functions requirements. We provide an evaluation of different configurations and a full error propagation study which ensures an accuracy of one unit in the last place. |
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ISSN: | 1939-8018 1939-8115 |
DOI: | 10.1007/s11265-008-0166-x |