Interface optimization for poly silicon/tungsten gates

Novel dual work function (DWF) based transistors featuring low gate resistances are presented. The process discussed enables extremely fast array timings easily and is thus key to fulfilling the performance requirements for high performance DRAM chips. The key enabler of the advanced gate integratio...

Full description

Saved in:
Bibliographic Details
Published in:Microelectronic engineering 2008-10, Vol.85 (10), p.2037-2041
Main Authors: Schmidbauer, Sven, Hahn, Jens, Buerke, Axel, Jakubowski, Frank, Storbeck, Olaf, Ting, Yu-Wei, Schuster, Thomas, Faul, Jürgen
Format: Article
Language:English
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Gate stack
Integrated circuits
Integrated circuits by function (including memories and processors)
Interface resistance
Microelectronic fabrication (materials and surfaces technology)
PVD
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Sputtering
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Novel dual work function (DWF) based transistors featuring low gate resistances are presented. The process discussed enables extremely fast array timings easily and is thus key to fulfilling the performance requirements for high performance DRAM chips. The key enabler of the advanced gate integration scheme and its properties is the understanding of tuning the interface contact resistance. The objective of this work was to systematically investigate the role of the interface between poly-Si and metal of DRAM gate structures focused on electrical data. Contact resistance values, speed and elemental analysis information summarize the main findings of the gate development and furthermore the stable control of the very thin film stack in high volume production.
ISSN:0167-9317
1873-5568
DOI:10.1016/j.mee.2008.07.010