Interface optimization for poly silicon/tungsten gates

Novel dual work function (DWF) based transistors featuring low gate resistances are presented. The process discussed enables extremely fast array timings easily and is thus key to fulfilling the performance requirements for high performance DRAM chips. The key enabler of the advanced gate integratio...

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Published in:Microelectronic engineering 2008-10, Vol.85 (10), p.2037-2041
Main Authors: Schmidbauer, Sven, Hahn, Jens, Buerke, Axel, Jakubowski, Frank, Storbeck, Olaf, Ting, Yu-Wei, Schuster, Thomas, Faul, Jürgen
Format: Article
Language:English
Subjects:
Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Gate stack
Integrated circuits
Integrated circuits by function (including memories and processors)
Interface resistance
Microelectronic fabrication (materials and surfaces technology)
PVD
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Sputtering
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cited_by cdi_FETCH-LOGICAL-c358t-c927d90721bf8239f2e3288b818293eac3c08e83e0f94070ae375433033b0ef13
cites cdi_FETCH-LOGICAL-c358t-c927d90721bf8239f2e3288b818293eac3c08e83e0f94070ae375433033b0ef13
container_end_page 2041
container_issue 10
container_start_page 2037
container_title Microelectronic engineering
container_volume 85
creator Schmidbauer, Sven
Hahn, Jens
Buerke, Axel
Jakubowski, Frank
Storbeck, Olaf
Ting, Yu-Wei
Schuster, Thomas
Faul, Jürgen
description Novel dual work function (DWF) based transistors featuring low gate resistances are presented. The process discussed enables extremely fast array timings easily and is thus key to fulfilling the performance requirements for high performance DRAM chips. The key enabler of the advanced gate integration scheme and its properties is the understanding of tuning the interface contact resistance. The objective of this work was to systematically investigate the role of the interface between poly-Si and metal of DRAM gate structures focused on electrical data. Contact resistance values, speed and elemental analysis information summarize the main findings of the gate development and furthermore the stable control of the very thin film stack in high volume production.
doi_str_mv 10.1016/j.mee.2008.07.010
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subjects Applied sciences
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Gate stack
Integrated circuits
Integrated circuits by function (including memories and processors)
Interface resistance
Microelectronic fabrication (materials and surfaces technology)
PVD
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Sputtering
title Interface optimization for poly silicon/tungsten gates
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