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Post electrochemical Cu deposition anneal impact on stress-voiding in individual vias
Stress-voiding is a critical reliability issue in Cu dual-damascene interconnects which could induce via openings. In our case, voids are typically observed at the edges at the bottom of vias. This location is correlated to a local delamination at Cu/Ta interface [E.T. Ogawa, J.W. McPherson, J.A. Ro...
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Published in: | Microelectronic engineering 2008-10, Vol.85 (10), p.2146-2149 |
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Main Authors: | , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | Stress-voiding is a critical reliability issue in Cu dual-damascene interconnects which could induce via openings. In our case, voids are typically observed at the edges at the bottom of vias. This location is correlated to a local delamination at Cu/Ta interface [E.T. Ogawa, J.W. McPherson, J.A. Rosal, M.J. Dickerson, T.-C. Chiu, L.Y. Tsung, M.K. Jain, T.D. Bonifield, J.C. Ondrusek, W.R. McKee, IEEE Int. Rel. Phys. Symp. Proc. (2002) 312–321; Y.K. Lim et al., Stress-induced voiding in multi-level copper/low-k interconnects, IEEE Int. Rel. Phys. Symp. Proc. (2004) 240–245]. Then, Cu/Ta interface properties at the bottom of via seem to be in the critical path for stress-voiding. In this paper, stress-voiding on 300
mm wafers in individual vias for different post electrochemical Cu deposition (ECD) anneals is studied. Electrical results show the clear benefit of hot plate and short furnace annealings. Microstructural characterizations indicate that impurities accumulation at Cu/Ta interface during long annealings could drive preferred void nucleation. |
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ISSN: | 0167-9317 1873-5568 |
DOI: | 10.1016/j.mee.2008.04.029 |