Power-constrained CMOS scaling limits

The scaling of CMOS technology has progressed reapidly for three decades, but many soon come to an end because of power-dissipation constraints. The primary problem is static prower dissipation, which is caused by leakage currents arising from quantum tunneling and thermal excitations.

Saved in:
Bibliographic Details
Published in:IBM journal of research and development 2002-03, Vol.46 (2-3), p.235-244
Main Author: Frank, D J
Format: Article
Language:English
Subjects:
Circuits
CMOS
Computer programming
Electrons
Monte Carlo simulation
Power
Citations: Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The scaling of CMOS technology has progressed reapidly for three decades, but many soon come to an end because of power-dissipation constraints. The primary problem is static prower dissipation, which is caused by leakage currents arising from quantum tunneling and thermal excitations.
ISSN:0018-8646
0018-8646
2151-8556
DOI:10.1147/rd.462.0235