A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition

A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase detector and automatic frequency locking technique is described. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase er...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2009-12, Vol.44 (12), p.3590-3602
Main Authors: Lee, Jri, Wu, Ke-Chung
Format: Article
Language:English
Subjects:
Automatic frequency control
Bit error rate (BER)
Circuits
clock and data recovery (CDR)
Clocks
CMOS
CMOS technology
Data recovery
Error analysis
frequency detector (FD)
Frequency locked loops
High speed
Jitter
jitter generation
jitter tolerance
Linear phase
linear phase detector (PD)
Phase detection
Phase error
Phase frequency detector
Space vector pulse width modulation
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Description
Summary:A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase detector and automatic frequency locking technique is described. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase error. The frequency acquisition loop utilizes the data phases rather than the clock phases to distill the frequency difference, and no external reference is used in this design. Fabricated in 90-nm CMOS technology, this circuit reveals rms and peak-to-peak jitter of 480 fs and 4.22 ps in response to a 2 31 -1 PRBS on the recovered clock while consuming 154 mW from a 1.5-V supply.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2009.2031042