A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

• Published in: IEEE journal of solid-state circuits 2010-01, Vol.45 (1), p.103-110
• Main Authors: Yih Wang, Bhattacharya, U., Hamzaoglu, F., Kolar, P., Yong-Gee Ng, Liqiong Wei, Ying Zhang, Zhang, K., Bohr, M.
• Format: Article
• Language: English
• Subjects: 32 nm; Applied sciences; CMOS logic circuits; CMOS memory integrated circuits; CMOS technology; Design. Technologies. Operation analysis. Testing; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Energy management; Exact sciences and technology; High K dielectric materials; high-k + metal-gate; High-K gate dielectrics; Integrated circuits; Integrated circuits by function (including memories and processors); Logic design; Power supplies; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; sleep transistor; static random-access memory (SRAM); Technology management; Transistors; variations; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2009.2034082

This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ¿m 2 six-transistor bitcell that supports a broad range of operating voltages for low-power and high-frequency embedded applications. The tileable 128 kb SRAM subarray achieves 72% array efficiency with 4.2 Mb/mm 2 bit density, and consumes 5 mW of leakage power at the supply voltage of 1 V. The design provides 4 GHz and 2 GHz of operating frequencies at the supply voltages of 1.0 V and 0.8 V, respectively. The integrated power management scheme features close-loop memory array leakage control, floating bitline, and wordline driver sleep transistor, resulting in a 58% reduction in subarray leakage power consumption.