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Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs
A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical c...
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| Published in: | IEEE transactions on nuclear science 2007-08, Vol.54 (4), p.935-945 |
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| Main Authors: | , , , , , , , , , |
| Format: | Article |
| Language: | English |
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| cites | cdi_FETCH-LOGICAL-c417t-831c9534f9d797a1c89e018241b0ab8cc26a05c921539ba91269d20297e0b2c43 |
| container_end_page | 945 |
| container_issue | 4 |
| container_start_page | 935 |
| container_title | IEEE transactions on nuclear science |
| container_volume | 54 |
| creator | Bajura, M.A. Boulghassoul, Y.. Naseer, R.. DasGupta, S.. Witulski, A.F. Sondeen, J.. Stansberry, S.D. Draper, J.. Massengill, L.W. Damoulakis, J.N. |
| description | A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Q crit ) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X ldquoprocess generationrdquo scaling penalty in area, speed, and power. |
| doi_str_mv | 10.1109/TNS.2007.892119 |
| format | article |
| fullrecord | <record><control><sourceid>proquest_ieee_</sourceid><recordid>TN_cdi_proquest_miscellaneous_36326282</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4291685</ieee_id><sourcerecordid>2544302521</sourcerecordid><originalsourceid>FETCH-LOGICAL-c417t-831c9534f9d797a1c89e018241b0ab8cc26a05c921539ba91269d20297e0b2c43</originalsourceid><addsrcrecordid>eNp9kT1PAzEMhiMEEqUwM7BEDDBda-cud8lYqkKRWpBoO0e5XNpedR8luQ78e1IVMTAwWZYf26_9EnKLMEAEOVy-LQYMIBsIyRDlGekh5yJCnolz0gNAEclEykty5f0upAkH3iOreVvYylPdFHRUbVpXdtu6NHRW1mXn6bp1oUQn43H0pL0NzH7vWm22tGvpVLvCNmWzoYtDHiFA1NR08TGa-2tysdaVtzc_sU9Wz5PleBrN3l9ex6NZZBLMukjEaCSPk7UsMplpNELaoJMlmIPOhTEs1cBNuIfHMtcSWSoLBkxmFnJmkrhPHk9zg6jPg_WdqktvbFXpxrYHr4SANEwGEciHf8k4jVnKBAvg_R9w1x5cE65QYT_y8F0I0PAEGdd67-xa7V1Za_elENTRDRXcUEc31MmN0HF36iittb90wiSmgsffRM-BhA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>912158920</pqid></control><display><type>article</type><title>Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs</title><source>IEEE Xplore (Online service)</source><creator>Bajura, M.A. ; Boulghassoul, Y.. ; Naseer, R.. ; DasGupta, S.. ; Witulski, A.F. ; Sondeen, J.. ; Stansberry, S.D. ; Draper, J.. ; Massengill, L.W. ; Damoulakis, J.N.</creator><creatorcontrib>Bajura, M.A. ; Boulghassoul, Y.. ; Naseer, R.. ; DasGupta, S.. ; Witulski, A.F. ; Sondeen, J.. ; Stansberry, S.D. ; Draper, J.. ; Massengill, L.W. ; Damoulakis, J.N.</creatorcontrib><description>A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Q crit ) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X ldquoprocess generationrdquo scaling penalty in area, speed, and power.</description><identifier>ISSN: 0018-9499</identifier><identifier>EISSN: 1558-1578</identifier><identifier>DOI: 10.1109/TNS.2007.892119</identifier><identifier>CODEN: IETNAE</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Algorithms ; Approximation ; Bit error rate ; Charge ; Circuits ; CMOS technology ; Error correction codes ; Error correction coding ; Government ; Hardening ; Mathematical model ; Mathematical models ; memory fault tolerance ; Power generation ; Protection ; radiation effects ; Random access memory ; Scrubbing ; Space environment ; Space technology ; Static random access memory</subject><ispartof>IEEE transactions on nuclear science, 2007-08, Vol.54 (4), p.935-945</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2007</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c417t-831c9534f9d797a1c89e018241b0ab8cc26a05c921539ba91269d20297e0b2c43</citedby><cites>FETCH-LOGICAL-c417t-831c9534f9d797a1c89e018241b0ab8cc26a05c921539ba91269d20297e0b2c43</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4291685$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,27905,27906,54777</link.rule.ids></links><search><creatorcontrib>Bajura, M.A.</creatorcontrib><creatorcontrib>Boulghassoul, Y..</creatorcontrib><creatorcontrib>Naseer, R..</creatorcontrib><creatorcontrib>DasGupta, S..</creatorcontrib><creatorcontrib>Witulski, A.F.</creatorcontrib><creatorcontrib>Sondeen, J..</creatorcontrib><creatorcontrib>Stansberry, S.D.</creatorcontrib><creatorcontrib>Draper, J..</creatorcontrib><creatorcontrib>Massengill, L.W.</creatorcontrib><creatorcontrib>Damoulakis, J.N.</creatorcontrib><title>Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs</title><title>IEEE transactions on nuclear science</title><addtitle>TNS</addtitle><description>A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Q crit ) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X ldquoprocess generationrdquo scaling penalty in area, speed, and power.</description><subject>Algorithms</subject><subject>Approximation</subject><subject>Bit error rate</subject><subject>Charge</subject><subject>Circuits</subject><subject>CMOS technology</subject><subject>Error correction codes</subject><subject>Error correction coding</subject><subject>Government</subject><subject>Hardening</subject><subject>Mathematical model</subject><subject>Mathematical models</subject><subject>memory fault tolerance</subject><subject>Power generation</subject><subject>Protection</subject><subject>radiation effects</subject><subject>Random access memory</subject><subject>Scrubbing</subject><subject>Space environment</subject><subject>Space technology</subject><subject>Static random access memory</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><recordid>eNp9kT1PAzEMhiMEEqUwM7BEDDBda-cud8lYqkKRWpBoO0e5XNpedR8luQ78e1IVMTAwWZYf26_9EnKLMEAEOVy-LQYMIBsIyRDlGekh5yJCnolz0gNAEclEykty5f0upAkH3iOreVvYylPdFHRUbVpXdtu6NHRW1mXn6bp1oUQn43H0pL0NzH7vWm22tGvpVLvCNmWzoYtDHiFA1NR08TGa-2tysdaVtzc_sU9Wz5PleBrN3l9ex6NZZBLMukjEaCSPk7UsMplpNELaoJMlmIPOhTEs1cBNuIfHMtcSWSoLBkxmFnJmkrhPHk9zg6jPg_WdqktvbFXpxrYHr4SANEwGEciHf8k4jVnKBAvg_R9w1x5cE65QYT_y8F0I0PAEGdd67-xa7V1Za_elENTRDRXcUEc31MmN0HF36iittb90wiSmgsffRM-BhA</recordid><startdate>20070801</startdate><enddate>20070801</enddate><creator>Bajura, M.A.</creator><creator>Boulghassoul, Y..</creator><creator>Naseer, R..</creator><creator>DasGupta, S..</creator><creator>Witulski, A.F.</creator><creator>Sondeen, J..</creator><creator>Stansberry, S.D.</creator><creator>Draper, J..</creator><creator>Massengill, L.W.</creator><creator>Damoulakis, J.N.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7QF</scope><scope>7QL</scope><scope>7QQ</scope><scope>7SC</scope><scope>7SE</scope><scope>7SP</scope><scope>7SR</scope><scope>7T7</scope><scope>7TA</scope><scope>7TB</scope><scope>7U5</scope><scope>7U9</scope><scope>8BQ</scope><scope>8FD</scope><scope>C1K</scope><scope>F28</scope><scope>FR3</scope><scope>H8D</scope><scope>H94</scope><scope>JG9</scope><scope>JQ2</scope><scope>KR7</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>M7N</scope><scope>P64</scope></search><sort><creationdate>20070801</creationdate><title>Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs</title><author>Bajura, M.A. ; Boulghassoul, Y.. ; Naseer, R.. ; DasGupta, S.. ; Witulski, A.F. ; Sondeen, J.. ; Stansberry, S.D. ; Draper, J.. ; Massengill, L.W. ; Damoulakis, J.N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c417t-831c9534f9d797a1c89e018241b0ab8cc26a05c921539ba91269d20297e0b2c43</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Algorithms</topic><topic>Approximation</topic><topic>Bit error rate</topic><topic>Charge</topic><topic>Circuits</topic><topic>CMOS technology</topic><topic>Error correction codes</topic><topic>Error correction coding</topic><topic>Government</topic><topic>Hardening</topic><topic>Mathematical model</topic><topic>Mathematical models</topic><topic>memory fault tolerance</topic><topic>Power generation</topic><topic>Protection</topic><topic>radiation effects</topic><topic>Random access memory</topic><topic>Scrubbing</topic><topic>Space environment</topic><topic>Space technology</topic><topic>Static random access memory</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Bajura, M.A.</creatorcontrib><creatorcontrib>Boulghassoul, Y..</creatorcontrib><creatorcontrib>Naseer, R..</creatorcontrib><creatorcontrib>DasGupta, S..</creatorcontrib><creatorcontrib>Witulski, A.F.</creatorcontrib><creatorcontrib>Sondeen, J..</creatorcontrib><creatorcontrib>Stansberry, S.D.</creatorcontrib><creatorcontrib>Draper, J..</creatorcontrib><creatorcontrib>Massengill, L.W.</creatorcontrib><creatorcontrib>Damoulakis, J.N.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><collection>Aluminium Industry Abstracts</collection><collection>Bacteriology Abstracts (Microbiology B)</collection><collection>Ceramic Abstracts</collection><collection>Computer and Information Systems Abstracts</collection><collection>Corrosion Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>Industrial and Applied Microbiology Abstracts (Microbiology A)</collection><collection>Materials Business File</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Virology and AIDS Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Environmental Sciences and Pollution Management</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Aerospace Database</collection><collection>AIDS and Cancer Research Abstracts</collection><collection>Materials Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Algology Mycology and Protozoology Abstracts (Microbiology C)</collection><collection>Biotechnology and BioEngineering Abstracts</collection><jtitle>IEEE transactions on nuclear science</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Bajura, M.A.</au><au>Boulghassoul, Y..</au><au>Naseer, R..</au><au>DasGupta, S..</au><au>Witulski, A.F.</au><au>Sondeen, J..</au><au>Stansberry, S.D.</au><au>Draper, J..</au><au>Massengill, L.W.</au><au>Damoulakis, J.N.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs</atitle><jtitle>IEEE transactions on nuclear science</jtitle><stitle>TNS</stitle><date>2007-08-01</date><risdate>2007</risdate><volume>54</volume><issue>4</issue><spage>935</spage><epage>945</epage><pages>935-945</pages><issn>0018-9499</issn><eissn>1558-1578</eissn><coden>IETNAE</coden><abstract>A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Q crit ) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X ldquoprocess generationrdquo scaling penalty in area, speed, and power.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TNS.2007.892119</doi><tpages>11</tpages></addata></record> |
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| identifier | ISSN: 0018-9499 |
| ispartof | IEEE transactions on nuclear science, 2007-08, Vol.54 (4), p.935-945 |
| issn | 0018-9499 1558-1578 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_36326282 |
| source | IEEE Xplore (Online service) |
| subjects | Algorithms Approximation Bit error rate Charge Circuits CMOS technology Error correction codes Error correction coding Government Hardening Mathematical model Mathematical models memory fault tolerance Power generation Protection radiation effects Random access memory Scrubbing Space environment Space technology Static random access memory |
| title | Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T02%3A57%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_ieee_&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Models%20and%20Algorithmic%20Limits%20for%20an%20ECC-Based%20Approach%20to%20Hardening%20Sub-100-nm%20SRAMs&rft.jtitle=IEEE%20transactions%20on%20nuclear%20science&rft.au=Bajura,%20M.A.&rft.date=2007-08-01&rft.volume=54&rft.issue=4&rft.spage=935&rft.epage=945&rft.pages=935-945&rft.issn=0018-9499&rft.eissn=1558-1578&rft.coden=IETNAE&rft_id=info:doi/10.1109/TNS.2007.892119&rft_dat=%3Cproquest_ieee_%3E2544302521%3C/proquest_ieee_%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c417t-831c9534f9d797a1c89e018241b0ab8cc26a05c921539ba91269d20297e0b2c43%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=912158920&rft_id=info:pmid/&rft_ieee_id=4291685&rfr_iscdi=true |